summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Add support for polynomial type, for polynomial multiplyNate Begeman2010-06-101-0/+2
| | | | llvm-svn: 105792
* Teach tablegen to allow "let" expressions inside multiclasses,Bruno Cardoso Lopes2010-06-102-53/+43
| | | | | | providing more ways to factor out commonality from the records. llvm-svn: 105776
* NEON support for _lane ops, and multiplies by scalar.Nate Begeman2010-06-102-45/+79
| | | | llvm-svn: 105769
* Further refine types for operations which take scalars.Nate Begeman2010-06-091-8/+8
| | | | | | This will be used primarily by NEON shift intrinsics. llvm-svn: 105733
* How about ULL...Eric Christopher2010-06-091-1/+1
| | | | llvm-svn: 105726
* Specialize I-Class instructions better so that we have less work to do in ↵Nate Begeman2010-06-091-4/+20
| | | | | | | | codegen. Parenthesize macro args llvm-svn: 105682
* Handle instructions which need to be #defines for the purpose of capturing ↵Nate Begeman2010-06-092-24/+62
| | | | | | | | constant arguments Handle extract hi/lo with common code llvm-svn: 105666
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-083-2/+10
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* Fix a valgrind error.Nate Begeman2010-06-081-1/+1
| | | | llvm-svn: 105600
* Refine BuiltinsARM.def types a bit, we should do a better job of this to ↵Nate Begeman2010-06-081-2/+4
| | | | | | save some c++ code in CGBuiltins. llvm-svn: 105598
* ARM NEON:Nate Begeman2010-06-082-11/+55
| | | | | | | fix vcvt naming handle vdup, vcombine with generic vector code llvm-svn: 105588
* clang codegen supportNate Begeman2010-06-071-73/+83
| | | | llvm-svn: 105531
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-052-9/+1
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-052-1/+9
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Teach tablegen to support 'defm' inside multiclasses.Bruno Cardoso Lopes2010-06-052-10/+42
| | | | llvm-svn: 105519
* Handle multi-vector returns and args.Nate Begeman2010-06-041-24/+71
| | | | llvm-svn: 105496
* Additional fixes to BuiltinsARM.def generator, on to clang codegen.Nate Begeman2010-06-041-9/+38
| | | | llvm-svn: 105488
* Progress on generating BuiltinsARM.def, still some duplicates to work out.Nate Begeman2010-06-041-3/+110
| | | | llvm-svn: 105461
* BuiltinsARM.def emitter, still needs a substantial bit of tweaking to ↵Nate Begeman2010-06-043-71/+119
| | | | | | lighten the load on clang. llvm-svn: 105456
* Mangle __builtin_neon_* names appropriately.Nate Begeman2010-06-042-30/+97
| | | | | | Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def llvm-svn: 105443
* Add some additional capabilities to the neon emitterNate Begeman2010-06-031-4/+31
| | | | llvm-svn: 105416
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-0/+7
| | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
* arm_neon.h now makes it through clang and generates appropriate code for ↵Nate Begeman2010-06-031-19/+112
| | | | | | | | those functions which can use generic vector operators rather than __builtin_neon_* llvm-svn: 105380
* arm_neon.h emitter now mostly complete for the purposes of initial testing.Nate Begeman2010-06-021-10/+81
| | | | llvm-svn: 105349
* Pacify recent gcc: remove a pointless const qualifier.Duncan Sands2010-06-021-1/+1
| | | | llvm-svn: 105318
* Checkpoint; handle 'int' and 'void' correctlyNate Begeman2010-06-021-25/+52
| | | | llvm-svn: 105316
* Emit full function prototypes. Definitions & typedefs to come.Nate Begeman2010-06-021-16/+72
| | | | llvm-svn: 105315
* Checkpoint arm_neon.h generation with tablegenNate Begeman2010-06-021-13/+241
| | | | llvm-svn: 105307
* Fix commentAlexis Hunt2010-06-011-1/+1
| | | | llvm-svn: 105297
* Allow for creation of clang DeclNodes tables.Alexis Hunt2010-05-303-52/+131
| | | | | | | | The StmtNodes generator has been generalized to allow for the creation of DeclNodes tables as well, and another emitter was added for DeclContexts. llvm-svn: 105164
* Emit TargetRegisterInfo::composeSubRegIndices().Jakob Stoklund Olesen2010-05-281-18/+114
| | | | | | Also verify that all subregister indices compose unambiguously. llvm-svn: 105064
* Comment out some code in prep for actual .td file checkpoint.Nate Begeman2010-05-281-3/+2
| | | | llvm-svn: 104927
* Fix build breakage.Eli Friedman2010-05-281-1/+1
| | | | llvm-svn: 104912
* Add support to tablegen for auto-generating arm_neon.h from a tablegen ↵Nate Begeman2010-05-284-0/+104
| | | | | | | | | | | description of the intrinsics. The goal is to auto-generate both support for GCC-style (vector) and ARM-style (struct of vector) intrinsics. This is work in progress, but will be completed soon. llvm-svn: 104910
* Simplify raw_ostream usage.Dan Gohman2010-05-271-45/+37
| | | | llvm-svn: 104874
* Minor code simplification.Dan Gohman2010-05-271-9/+9
| | | | llvm-svn: 104845
* AsmMatcher: Ensure classes are totally ordered, so we can std::sort them ↵Daniel Dunbar2010-05-271-1/+10
| | | | | | reliably. llvm-svn: 104806
* Check that inherited subregisters all have a direct SubRegIndex.Jakob Stoklund Olesen2010-05-261-2/+25
| | | | llvm-svn: 104755
* Add StringRef::compare_numeric and use it to sort TableGen register records.Jakob Stoklund Olesen2010-05-262-1/+3
| | | | | | | This means that our Registers are now ordered R7, R8, R9, R10, R12, ... Not R1, R10, R11, R12, R2, R3, ... llvm-svn: 104745
* Suppress emmission of empty subreg/superreg/alias sets.Jakob Stoklund Olesen2010-05-261-3/+9
| | | | llvm-svn: 104741
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-36/+83
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-83/+36
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-36/+83
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-251-84/+5
| | | | llvm-svn: 104650
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-251-1/+12
| | | | llvm-svn: 104628
* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-252-3/+6
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. llvm-svn: 104615
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-6/+9
| | | | llvm-svn: 104571
* diaggroup categories should take precedence over diag-specific groups.Chris Lattner2010-05-241-8/+9
| | | | llvm-svn: 104567
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-244-82/+114
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-244-12/+46
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. llvm-svn: 104492
OpenPOWER on IntegriCloud