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* Added instregex support to TableGen subtarget emitter.Andrew Trick2012-10-033-10/+84
| | | | | | | | This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. llvm-svn: 165180
* TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick2012-10-033-130/+229
| | | | | | | | | A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. llvm-svn: 165179
* Cleanup TableGen subtarget emitter.Andrew Trick2012-10-032-6/+7
| | | | llvm-svn: 165178
* [ms-inline asm] Default to the 'm' constraint. This matches the behavior of theChad Rosier2012-10-031-3/+3
| | | | | | MSVC compiler. llvm-svn: 165174
* tblgen: Migrate llvm-tblgen to new TableGenMain API.Sean Silva2012-10-031-82/+77
| | | | llvm-svn: 165166
* Fix 80-column violations. Cleanup whitespace in generated code.Chad Rosier2012-10-021-15/+23
| | | | llvm-svn: 164983
* [ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier2012-10-011-45/+38
| | | | | | | | | | | map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. llvm-svn: 164979
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-272-2/+2
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-272-2/+2
| | | | llvm-svn: 164767
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-6/+6
| | | | | | Also remove an unused argument. llvm-svn: 164567
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-2/+2
| | | | llvm-svn: 164548
* Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick2012-09-223-87/+295
| | | | | | | Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. llvm-svn: 164451
* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-211-2/+2
| | | | llvm-svn: 164420
* Whitespace.Chad Rosier2012-09-211-2/+2
| | | | llvm-svn: 164406
* Add in new data types that are used by AMDIL/ANL among others.Micah Villmow2012-09-191-0/+8
| | | | llvm-svn: 164261
* Soften the pattern-can-never-match error in TableGen into a warning. This ↵Owen Anderson2012-09-191-2/+5
| | | | | | pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). llvm-svn: 164256
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-192-19/+2
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick2012-09-193-7/+44
| | | | llvm-svn: 164199
* Iterate deterministicaly over ClassInfo*'sSean Silva2012-09-191-2/+12
| | | | | | | | Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. llvm-svn: 164191
* Iterate deterministically over register classesSean Silva2012-09-191-2/+3
| | | | | | | | Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. llvm-svn: 164190
* Refactor Record* by-ID comparator to Record.hSean Silva2012-09-192-18/+9
| | | | | | | | | | | This is a generally useful utility; there's no reason to have it hidden in CodeGenDAGPatterns.cpp. Also, rename it to fit the other comparators in Record.h Review by Jakob. llvm-svn: 164189
* Make custom operand parsing mnemonic indices use the same mnemonic table as ↵Craig Topper2012-09-181-34/+39
| | | | | | the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. llvm-svn: 164109
* Use variable type for index into mnemonic table. Shrinks size of index field ↵Craig Topper2012-09-181-5/+14
| | | | | | on in tree targets. Saving static data space. llvm-svn: 164108
* Replaced ReInitMCSubtargetInfo with InitMCProcessor.Andrew Trick2012-09-181-1/+2
| | | | | | | | Now where we used to call ReInitMCSubtargetInfo, we actually recompute the same information as InitMCSubtargetInfo instead of only setting the feature bits. llvm-svn: 164105
* comment typoAndrew Trick2012-09-181-1/+1
| | | | llvm-svn: 164097
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-182-11/+1
| | | | llvm-svn: 164096
* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-181-0/+84
| | | | | | resolving instruction variants. llvm-svn: 164095
* TableGen subtarget emitter. Remove unnecessary header dependence.Andrew Trick2012-09-181-0/+1
| | | | llvm-svn: 164094
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-6/+25
| | | | | | model. llvm-svn: 164092
* Mark asm matcher conversion table as const.Craig Topper2012-09-181-5/+5
| | | | llvm-svn: 164088
* Fix typo in comment. No functional change.Craig Topper2012-09-181-1/+1
| | | | llvm-svn: 164086
* Backout the wrong subtarget emitter fixAndrew Trick2012-09-171-1/+1
| | | | llvm-svn: 164078
* Fix release build after revertingAndrew Trick2012-09-171-2/+1
| | | | llvm-svn: 164075
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-173-113/+20
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* InitMCProcessorAndrew Trick2012-09-171-1/+2
| | | | llvm-svn: 164066
* comment typoAndrew Trick2012-09-171-1/+1
| | | | llvm-svn: 164064
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-172-11/+1
| | | | llvm-svn: 164063
* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-171-0/+84
| | | | | | resolving instruction variants. llvm-svn: 164062
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-7/+25
| | | | | | model. llvm-svn: 164061
* TableGen subtarget emitter. Format and emit data tables for the new machine ↵Andrew Trick2012-09-171-6/+117
| | | | | | model. llvm-svn: 164060
* TableGen subtarget emitter. Generate data tables for the new machine model.Andrew Trick2012-09-171-2/+291
| | | | | | | | | | | | Map the CodeGenSchedule object model onto data tables. The structure of the data tables is defined in MC, so for convenience we include MCSchedule.h. The alternative is maintaining a redundant copy of the table structure definitions. Mapping the object model onto data tables is sufficiently complicated that it should not be interleaved with emitting source code. This avoids major problem with the backend for itinerary generation. llvm-svn: 164059
* TableGen subtarget emitter. Emit processor resources for the new machine model.Andrew Trick2012-09-171-10/+63
| | | | llvm-svn: 164058
* TableGen subtarget parser: Add getProcResourcesIdx().Andrew Trick2012-09-171-0/+10
| | | | llvm-svn: 164057
* TableGen: Add initializer.Jim Grosbach2012-09-171-1/+1
| | | | | | | Keep GCC's warnings happy. It can't reason out that the state machine won't ever hit the potentially uninitialized use in OPC_FilterValue. llvm-svn: 164041
* Fix typoMichael Liao2012-09-171-1/+1
| | | | llvm-svn: 164012
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-5/+6
| | | | llvm-svn: 164002
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-7/+7
| | | | llvm-svn: 163999
* Fix Doxygen issues: wrap code examples in \code and use \p to refer toDmitri Gribenko2012-09-151-4/+4
| | | | | | parameters. llvm-svn: 163984
* Revert r163878 as it breaks on targets with alternate register names. Such ↵Craig Topper2012-09-152-6/+4
| | | | | | targets do not exist in the main tree so this was not noticed. llvm-svn: 163959
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-152-0/+219
| | | | | | Collect processor resources from the subtarget defs. llvm-svn: 163953
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