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* Add a TODO.Mikhail Glushenkov2011-04-241-0/+2
| | | | llvm-svn: 130092
* Remove unused STL header includes.Jay Foad2011-04-238-10/+0
| | | | llvm-svn: 130068
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+5
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* Define Neon load/store intrinsics for Clang as macros instead of functions.Bob Wilson2011-04-221-15/+51
| | | | | | | This is needed so the front-end can see "aligned" attributes on the type for the pointer arguments. Radar 9311427. llvm-svn: 129964
* Don't allow per-register spill size and alignment.Jakob Stoklund Olesen2011-04-212-3/+0
| | | | | | | These values were not used for anything. Spill size and alignment is a property of the register class, not the register. llvm-svn: 129906
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-203-3/+6
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* Invert the meaning of printAliasInstr's return value. It now returnsEric Christopher2011-04-181-4/+4
| | | | | | true on success and false on failure. Update callers. llvm-svn: 129722
* Enhance the fixed-length disassembler to support the callbacks necessary for ↵Owen Anderson2011-04-181-5/+10
| | | | | | symbolic disassembly. llvm-svn: 129708
* Add a new bit that ImmLeaf's can opt into, which allows them to duck out ofChris Lattner2011-04-181-2/+10
| | | | | | | | the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. llvm-svn: 129692
* Implement major new fastisel functionality: the matcher can now handle ↵Chris Lattner2011-04-182-51/+233
| | | | | | | | | | | | | | | | | | | | | | | immediates with value constraints on them (when defined as ImmLeaf's). This is particularly important for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand, which has a value constraint. Before this patch we ended up iseling the examples into such amazing code as: movabsq $7, %rax imulq %rax, %rdi movq %rdi, %rax ret now we produce: imulq $7, %rdi, %rax ret This dramatically shrinks the generated code at -O0 on x86-64. llvm-svn: 129691
* introduce a new OpKind abstraction which wraps up operand flavors in a tidy ↵Chris Lattner2011-04-171-22/+48
| | | | | | | | little wrapper. No functionality change. llvm-svn: 129680
* change OperandsSignature to use SmallVector<char> instead of std::vector<string>Chris Lattner2011-04-172-16/+17
| | | | | | since the strings are always exactly one character, and there are usually only 2-3 operands. llvm-svn: 129678
* since the VT is fixed for a ImmLeaf, there is no reason to expose it to the ↵Chris Lattner2011-04-171-2/+0
| | | | | | matching code. llvm-svn: 129677
* now that predicates have a decent abstraction layer on them, introduce a new Chris Lattner2011-04-173-3/+26
| | | | | | | | | kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. llvm-svn: 129675
* Rework our internal representation of node predicates to expose moreChris Lattner2011-04-175-60/+139
| | | | | | | | structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. llvm-svn: 129670
* remove some debugging code I added.Chris Lattner2011-04-171-5/+0
| | | | llvm-svn: 129668
* 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner2011-04-171-9/+16
| | | | | | | | | | 2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. llvm-svn: 129666
* Initial work to improve documentation for Clang's diagnostics, from Matthieu ↵Douglas Gregor2011-04-153-3/+74
| | | | | | Monrocq llvm-svn: 129613
* Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some ↵Evan Cheng2011-04-151-6/+12
| | | | | | targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332 llvm-svn: 129590
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-155-10/+10
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Add an option to not print the alias of an instruction. It defaults to "printBill Wendling2011-04-131-0/+2
| | | | | | the alias". llvm-svn: 129485
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+4
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* TableGen: Keep the order of DECL_CONTEXT() for DeclNodes.td. RecordVector ↵NAKAMURA Takumi2011-04-111-4/+7
| | | | | | | | may be used instead of RecordSet. The result of DeclNodes.inc was unstable on msys, Windows 7 x64. llvm-svn: 129317
* Only emit the AvailableFeatures variable if it's used.Bill Wendling2011-04-081-4/+7
| | | | llvm-svn: 129124
* Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling2011-04-071-146/+59
| | | | | | | | | | | | | with the newer, cleaner model. It uses the IAPrinter class to hold the information that is needed to match an instruction with its alias. This also takes into account the available features of the platform. There is one bit of ugliness. The way the logic determines if a pattern is unique is O(N**2), which is gross. But in reality, the number of items it's checking against isn't large. So while it's N**2, it shouldn't be a massive time sink. llvm-svn: 129110
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-044-10/+31
| | | | llvm-svn: 128826
* Use array_lengthofJoerg Sonnenberger2011-04-041-2/+3
| | | | llvm-svn: 128823
* Change loops to derive the number of tables automaticallyJoerg Sonnenberger2011-04-041-2/+2
| | | | llvm-svn: 128818
* tlbgen/MC: StringRef's to temporary objects considered harmful.Daniel Dunbar2011-04-011-3/+3
| | | | llvm-svn: 128735
* Add annotations to tablegen-generated processor itineraries, or replace them ↵Andrew Trick2011-04-012-16/+21
| | | | | | with something meaningful. I want to be able to read and debug the generated tables. llvm-svn: 128703
* whitespaceAndrew Trick2011-04-012-68/+68
| | | | llvm-svn: 128701
* Use intrinsics for Neon vmull operations. Radar 9208957.Bob Wilson2011-03-312-27/+17
| | | | llvm-svn: 128591
* ClangSAEmClangSACheckersEmitter, emit info about groups.Argyrios Kyrtzidis2011-03-301-64/+79
| | | | llvm-svn: 128515
* Quiet a gcc warning about changed name lookup rulesMatt Beaumont-Gay2011-03-291-2/+2
| | | | llvm-svn: 128497
* In ClangSACheckersEmitter:Argyrios Kyrtzidis2011-03-291-7/+61
| | | | | | | - Also emit a list of packages and groups sorted by name - Avoid iterating over DenseSet so that the output of the arrays is deterministic. llvm-svn: 128489
* For ClangSACheckersEmitter, allow a package to belong to checker group, in ↵Argyrios Kyrtzidis2011-03-291-8/+28
| | | | | | which all its checkers will go into the group. llvm-svn: 128474
* Extend Clang's TableGen emitter for attributes to support bool arguments.Douglas Gregor2011-03-261-0/+2
| | | | llvm-svn: 128330
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen2011-03-251-0/+5
| | | | | | instructions, and add a test case for that. llvm-svn: 128249
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen2011-03-241-2/+2
| | | | | | | | | stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. llvm-svn: 128247
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-241-0/+5
| | | | | | | According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. llvm-svn: 128246
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-0/+4
| | | | llvm-svn: 128236
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-0/+4
| | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
* Update the Clang attribute emitter to handle attributes of 'version'Douglas Gregor2011-03-231-0/+46
| | | | | | | kind, and fix serialization/deserialization of IdentifierInfo attributes. These are requires for the new 'availability' attribute. llvm-svn: 128130
* Call static functions so that they aren't left unused.Bill Wendling2011-03-211-2/+4
| | | | llvm-svn: 128020
* A WIP commit of the InstAlias printing cleanup. This code will soon replace theBill Wendling2011-03-211-19/+121
| | | | | | | code below it. Even though it looks very similar, it will match more precisely and geneate better functions in the long run. llvm-svn: 127991
* Add the IAPrinter class.Bill Wendling2011-03-211-0/+97
| | | | | | | This is a helper class that will make it easier to say which InstAliases can be printed and which cannot (because of ambiguity). llvm-svn: 127990
* * Add classes that support the "feature" information.Bill Wendling2011-03-212-5/+120
| | | | | | * Move the code that emits the reg in reg class matching into its own function. llvm-svn: 127988
* Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson2011-03-181-0/+1
| | | | llvm-svn: 127888
* - Add "Bitcast" target instruction property for instructions which performEvan Cheng2011-03-154-9/+40
| | | | | | | nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. llvm-svn: 127667
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-153-52/+250
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
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