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* capture implicit uses and defs in CodeGenInstructionChris Lattner2010-03-182-0/+6
| | | | llvm-svn: 98879
* simplify this code, the # of sets in the pattern for an instructionChris Lattner2010-03-181-2/+1
| | | | | | shouldn't change this. llvm-svn: 98872
* disallow concatenation of two dags with different operators.Chris Lattner2010-03-181-12/+2
| | | | llvm-svn: 98871
* rewrite this to not artificially force concat the ins/outs list.Chris Lattner2010-03-181-13/+20
| | | | llvm-svn: 98870
* eliminate support for "ops" in the input/output list of anChris Lattner2010-03-181-4/+2
| | | | | | instruction. Instructions must use 'ins' and 'outs' now. llvm-svn: 98868
* remove some code that was working around old sparc v9 backend bugs.Chris Lattner2010-03-183-22/+24
| | | | | | Add checking that the input/output operand list in spelled right. llvm-svn: 98865
* MC/AsmMatcher: Add support for target specific "instruction cleanup" functions,Daniel Dunbar2010-03-181-5/+11
| | | | | | to allow custom post-processing of matched instructions. llvm-svn: 98857
* Add an extra newline to separate PP directives from the contentsKovarththanan Rajaratnam2010-03-181-1/+1
| | | | llvm-svn: 98820
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-164-1807/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-164-0/+1807
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* don't form a RecordChild or CheckChildType for child #'s over 7, we don'tChris Lattner2010-03-161-3/+5
| | | | | | have enums for them. llvm-svn: 98597
* eliminate some #if 0 code I added in r96905, type inference Chris Lattner2010-03-151-18/+0
| | | | | | now enforces that input/output named values have hte same type. llvm-svn: 98535
* Completely rewrite tblgen's type inference mechanism,Chris Lattner2010-03-157-458/+733
| | | | | | | | | | | | | | | | | | | | | | | | changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! llvm-svn: 98534
* Check in tablegen changes to fix disassembler related failures caused by r98465.Evan Cheng2010-03-142-0/+5
| | | | llvm-svn: 98468
* Node arguments to type casts can have names too. This codeChris Lattner2010-03-081-0/+8
| | | | | | | | | | | needs to be majorly refactored, but this spot bugfix allows things like: def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v4i32 node:$lhs), node:$rhs), [{ ... llvm-svn: 97952
* turn off debug spewChris Lattner2010-03-071-2/+2
| | | | llvm-svn: 97912
* more factoring.Chris Lattner2010-03-072-32/+34
| | | | llvm-svn: 97911
* teach tblgen to be more aggressive when factoring CheckType nodes.Chris Lattner2010-03-071-29/+95
| | | | | | | | | | | | | | | | | | | | | | Now it will factor things like this: CheckType i32 ... CheckOpcode ISD::AND CheckType i64 ... into: SwitchType: i32: ... i64: CheckOpcode ISD::AND ... This shrinks hte table by a few bytes, nothing spectacular. llvm-svn: 97908
* add some helper functions and implement isContradictory Chris Lattner2010-03-072-0/+99
| | | | | | | | for CheckValueTypeMatcher. The isContradictory implementation helps us factor better, shrinking x86 table from 79144 -> 78896 bytes. llvm-svn: 97905
* Make it not an error to specify -O* options several times.Mikhail Glushenkov2010-03-051-19/+57
| | | | | | As in 'llvmc -O2 -O2 test.c'. llvm-svn: 97787
* so hey, it turns out that the histogram was completely wrong, becauseChris Lattner2010-03-041-10/+32
| | | | | | | we sometimes emit nodes multiple times to string buffers to size them. Compute the histogram correctly. llvm-svn: 97708
* zap fixme.Chris Lattner2010-03-041-4/+0
| | | | llvm-svn: 97705
* now that complexpatterns are all emitted at the end of the matchChris Lattner2010-03-041-4/+3
| | | | | | | | sequence, just emit instruction predicates right before them. This exposes yet more factoring opportunitites, shrinking the X86 table to 79144 bytes. llvm-svn: 97704
* change the new isel matcher to emit ComplexPattern matchesChris Lattner2010-03-043-37/+92
| | | | | | | | | | as the very last thing before node emission. This should dramatically reduce the number of times we do 'MatchAddress' on X86, speeding up compile time. This also improves comments in the tables and shrinks the table a bit, now down to 80506 bytes for x86. llvm-svn: 97703
* enhance comment output to specify what recorded slotChris Lattner2010-03-043-5/+12
| | | | | | numbers a ComplexPat will match into. llvm-svn: 97696
* introduce a new SwitchTypeMatcher node (which is analogous toChris Lattner2010-03-034-21/+111
| | | | | | | | SwitchOpcodeMatcher) and have DAGISelMatcherOpt form it. This speeds up selection, particularly for X86 which has lots of variants of instructions with only type differences. llvm-svn: 97645
* the sorting predicate should work for comparing an elementChris Lattner2010-03-021-1/+1
| | | | | | to itself, even though this isn't wildly useful. llvm-svn: 97574
* eliminate CodeGen/DAGISelHeader.h, it is empty now.Chris Lattner2010-03-021-4/+0
| | | | llvm-svn: 97556
* Rewrite chain handling validation and input TokenFactor handlingChris Lattner2010-03-024-58/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | stuff now that we don't care about emulating the old broken behavior of the old isel. This eliminates the 'CheckChainCompatible' check (along with IsChainCompatible) which did an incorrect and inefficient scan *up* the chain nodes which happened as the pattern was being formed and does the validation at the end in HandleMergeInputChains when it forms a structural pattern. This scans "down" the graph, which means that it is quickly bounded by nodes already selected. This also handles token factors that get "trapped" in the dag. Removing the CheckChainCompatible nodes also shrinks the generated tables by about 6K for X86 (down to 83K). There are two pieces remaining before I can nuke PreprocessRMW: 1. I xfailed a test because we're now producing worse code in a case that has nothing to do with the change: it turns out that our use of MorphNodeTo will leave dead nodes in the graph which (depending on how the graph is walked) end up causing bogus uses of chains and blocking matches. This is really bad for other reasons, so I'll fix this in a follow-up patch. 2. CheckFoldableChainNode needs to be improved to handle the TF. llvm-svn: 97539
* add some missing \n'sChris Lattner2010-03-021-11/+19
| | | | llvm-svn: 97527
* fixme resolved.Chris Lattner2010-03-011-3/+0
| | | | llvm-svn: 97517
* remove a little hack I did for the old isel, not neededChris Lattner2010-03-011-4/+0
| | | | | | now that it is gone. llvm-svn: 97516
* resolve some fixmesChris Lattner2010-03-011-10/+3
| | | | llvm-svn: 97515
* resolve a fixme and simplify code by moving insertion of theChris Lattner2010-03-011-18/+8
| | | | | | | | EmitMergeInputChainsMatcher node up into EmitResultCode. This doesn't have much of an effect on the generated code, the X86 table is exactly the same size. llvm-svn: 97514
* resolve a fixme by having the .td file parser reject thigns likeChris Lattner2010-03-014-12/+14
| | | | | | | | (set GPR, somecomplexpattern) if somecomplexpattern doesn't declare what it can match. llvm-svn: 97513
* remove dead code, simplify.Chris Lattner2010-03-011-10/+4
| | | | llvm-svn: 97510
* Fix PR2590 by making PatternSortingPredicate actually be Chris Lattner2010-03-014-8/+22
| | | | | | | | | | | | | | | ordered correctly. Previously it would get in trouble when two patterns were too similar and give them nondet ordering. We force this by using the record ID order as a fallback. The testsuite diff is due to alpha patterns being ordered slightly differently, the change is a semantic noop afaict: < lda $0,-100($16) --- > subq $16,100,$0 llvm-svn: 97509
* tolerate factoring the *last* node for CellSPU.Chris Lattner2010-03-011-0/+5
| | | | llvm-svn: 97508
* optimize tblgen compile time by eliminating the old isel.Chris Lattner2010-03-012-1770/+3
| | | | llvm-svn: 97504
* don't emit the old sdnodexform stuff for the new isel.Chris Lattner2010-03-011-2/+2
| | | | llvm-svn: 97486
* Turn on the new isel by default. Here are some fun numbersChris Lattner2010-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | with a release-asserts build on x86-64-darwin10: LLC Size: Old: 15,426,852 New: 12,759,140 (down 2.7M) LLI Size: Old: 9,926,876 New: 8,864,292 (down 1.1M) X86ISelDAGToDAG.o size: Old: 1,401,232 New: 162,868 (down 1.3M) Time to build X86ISelDAGToDAG.o: Old: 67.147u 2.060s 1:09.78 New: 4.234u 0.387s 0:04.77 llvm-svn: 97475
* Missed a \n in previous commit.Torok Edwin2010-03-011-0/+1
| | | | llvm-svn: 97472
* Add command-line flag to tblgen to turn off generating comments for the newTorok Edwin2010-03-011-57/+117
| | | | | | | isel (defaults it to generate comments). This reduces the size of the generated source file. llvm-svn: 97470
* Emit type checks late instead of early, this encouragesChris Lattner2010-03-011-1/+6
| | | | | | | structural matching code to be factored and shared this shrinks the X86 isel table from 86537 to 83890 bytes. llvm-svn: 97442
* Emit a redundant check for immediates at root context, e.g. (imm 0).Chris Lattner2010-03-012-2/+10
| | | | | | | | This allows formation of OpcodeSwitch for top level patterns, in particular on X86. This saves about 1K of data space in the x86 table and makes the dispatch much more efficient. llvm-svn: 97440
* eliminate the CheckMultiOpcodeMatcher code and have each Chris Lattner2010-03-016-78/+46
| | | | | | | | | ComplexPattern at the root be generated multiple times, once for each opcode they are part of. This encourages factoring because the opcode checks get treated just like everything else in the matcher. llvm-svn: 97439
* add a new OPC_SwitchOpcode which is semantically equivalentChris Lattner2010-03-014-11/+149
| | | | | | | | | | | | to a scope where every child starts with a CheckOpcode, but executes more efficiently. Enhance DAGISelMatcherOpt to form it. This also fixes a bug in CheckOpcode: apparently the SDNodeInfo objects are not pointer comparable, we have to compare the enum name. llvm-svn: 97438
* pull MarkFlagResult out from between an EmitNode/CompleteMatchChris Lattner2010-03-011-1/+17
| | | | | | | pair. This encourages MorphNodeTo formation, this gets us 200 more MorphNodeTo's on X86 and shrinks the table a bit. llvm-svn: 97434
* enhance RecordNode and RecordChild comments to indicate whatChris Lattner2010-03-014-12/+30
| | | | | | slot they're recording into, no functionality change. llvm-svn: 97433
* Emit redundant opcode checks for andimm and orimm tests at rootChris Lattner2010-03-012-0/+27
| | | | | | | | | | | so that we get grouping at the top level. Add an optimization to reorder type check & record nodes after opcode checks. We prefer to expose tree shape matching which improves grouping and will enhance the next optimization. llvm-svn: 97432
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