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* Another instance where GCC doesn't understand implicit construction of ↵Benjamin Kramer2017-03-241-2/+2
| | | | | | StringLiteral. llvm-svn: 298703
* Make GCC happy again.Benjamin Kramer2017-03-241-1/+1
| | | | llvm-svn: 298702
* Don't build up std::vectors with constant sizes when an array suffices.Benjamin Kramer2017-03-241-75/+70
| | | | | | NFC. llvm-svn: 298701
* Move spill size and alignment info from MC to TargetRegisterInfoKrzysztof Parzyszek2017-03-231-4/+4
| | | | | | | | | This is another step towards implementing register classes with parametrized register/spill sizes. Differential Revision: https://reviews.llvm.org/D31299 llvm-svn: 298652
* Rename AttributeSet to AttributeListReid Kleckner2017-03-211-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This class is a list of AttributeSetNodes corresponding the function prototype of a call or function declaration. This class used to be called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is typically accessed by parameter and return value index, so "AttributeList" seems like a more intuitive name. Rename AttributeSetImpl to AttributeListImpl to follow suit. It's useful to rename this class so that we can rename AttributeSetNode to AttributeSet later. AttributeSet is the set of attributes that apply to a single function, argument, or return value. Reviewers: sanjoy, javed.absar, chandlerc, pete Reviewed By: pete Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits Differential Revision: https://reviews.llvm.org/D31102 llvm-svn: 298393
* GlobalISel: add implicit defs & uses when mutating an instruction.Tim Northover2017-03-201-1/+18
| | | | | | Otherwise a scheduler might do bad things to the code we produce. llvm-svn: 298311
* Explicitly add move constructor/assignment operators.Zachary Turner2017-03-201-0/+2
| | | | | | | | | | These are needed due to some obscure rules in the standard about how std::vector selects between copy and move constructors, which can cause a conforming implementation to attempt to select the copy constructor of RuleMatcher, which will fail since std::unique_ptr<> isn't copyable. llvm-svn: 298294
* [tablegen][globalisel] Capture instructions into locals and related ↵Daniel Sanders2017-03-201-60/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | infrastructure for multiple instructions matches. Summary: Prepare the way for nested instruction matching support by having actions like CopyRenderer look up operands in the RuleMatcher rather than a specific InstructionMatcher. This allows actions to reference any operand from any matched instruction. It works by checking the 'shape' of the match and capturing each matched instruction to a local variable. If the shape is wrong (not enough operands, leaf nodes where non-leafs are expected, etc.), then the rule exits early without checking the predicates. Once we've captured the instructions, we then test the predicates as before (except using the local variables). If the match is successful, then we render the new instruction as before using the local variables. It's not noticable in this patch but by the time we support multiple instruction matching, this patch will also cause a significant improvement to readability of the emitted code since MRI.getVRegDef(I->getOperand(0).getReg()) will simply be MI1 after emitCxxCaptureStmts(). This isn't quite NFC because I've also fixed a bug that I'm surprised we haven't encountered yet. It now checks there are at least the expected number of operands before accessing them with getOperand(). Depends on D30531 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: rovka Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30535 llvm-svn: 298257
* Removed unnecessary semicolon. NFCI.Simon Pilgrim2017-03-151-1/+1
| | | | llvm-svn: 297906
* [tablegen][globalisel] Trivial changes to reduce size of following patch. NFC.Daniel Sanders2017-03-151-77/+90
| | | | | | | | | | | | | | | | | | Summary: * Move namespace { * Trivial: Typo * RuleMatcher: Separate class and definition * Trivial: const findNodeEquiv Reviewers: t.p.northover, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: rovka Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30531 llvm-svn: 297884
* [globalisel][tblgen] Add support for ComplexPatternsDaniel Sanders2017-03-141-14/+245
| | | | | | | | | | | | | | | | | | | Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
* [SelectionDAG] Enhance SDTCisSameNumEltsAs to work with scalar types and use ↵Craig Topper2017-03-132-38/+57
| | | | | | | | | | | | it on extend/trunc/round operations. Currently we don't enforce that ISD::ANY_EXTEND, ZERO_EXTEND, SIGN_EXTEND, TRUNC, FP_ROUND, FP_EXTEND have the same number of elements(including scalar) between their input and output. Though we have them documented as such. Up until a few months ago x86 created nodes that violated this rule. That's all been fixed now, and we should enforce the rule going forward. In order to do this we need to allow SDTCisSameNumEltsAs to support scalar types and not enforce being a vector. If one type is scalar we will force the other type to also be scalar. Differential Revision: https://reviews.llvm.org/D30878 llvm-svn: 297648
* [ADT] Improve the genericity of llvm::enumerate().Zachary Turner2017-03-131-2/+2
| | | | | | | | | | | | | | There were some issues in the implementation of enumerate() preventing it from being used in various contexts. These were all related to the fact that it did not supporter llvm's iterator_facade_base class. So this patch adds support for that and additionally exposes a new helper method to_vector() that will evaluate an entire range and store the results in a vector. Differential Revision: https://reviews.llvm.org/D30853 llvm-svn: 297633
* Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both ↵Craig Topper2017-03-131-3/+2
| | | | | | | | | | have a memory operand. We should just continue to check other operands instead." This reverts r297596. There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table. llvm-svn: 297602
* [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a ↵Craig Topper2017-03-131-2/+3
| | | | | | | | memory operand. We should just continue to check other operands instead. This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch. llvm-svn: 297596
* [X86] Minor formatting tweaks in EVEX to VEX tables. NFCCraig Topper2017-03-131-45/+45
| | | | llvm-svn: 297595
* [SelectionDAG] Make SelectCode return voidJoey Gouly2017-03-091-2/+1
| | | | | | | | | | | SelectCode has been returning nullptr since 182dac0 ("SDAG: Make SelectCodeCommon return void", 2016-05-10). Make SelectCode also return void instead, as all callers have been updated. Patch by Sven van Haastregt. Review: https://reviews.llvm.org/D30497 llvm-svn: 297377
* Recommit: [globalisel] Change LLT constructor string into an LLT-based ↵Daniel Sanders2017-03-071-16/+35
| | | | | | | | | | | | | | | | | | | | object that knows how to generate it. Summary: This will allow future patches to inspect the details of the LLT. The implementation is now split between the Support and CodeGen libraries to allow TableGen to use this class without introducing layering concerns. Thanks to Ahmed Bougacha for finding a reasonable way to avoid the layering issue and providing the version of this patch without that problem. The problem with the previous commit appears to have been that TableGen was including CodeGen/LowLevelType.h instead of Support/LowLevelTypeImpl.h. Reviewers: t.p.northover, qcolombet, rovka, aditya_nandakumar, ab, javed.absar Subscribers: arsenm, nhaehnle, mgorny, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30046 llvm-svn: 297241
* Revert r297177: Change LLT constructor string into an LLT-based object ...Daniel Sanders2017-03-071-35/+16
| | | | | | | | | | More module problems. This time it only showed up in the stage 2 compile of clang-x86_64-linux-selfhost-modules-2 but not the stage 1 compile. Somehow, this change causes the build to need Attributes.gen before it's been generated. llvm-svn: 297188
* [globalisel] Change LLT constructor string into an LLT-based object that ↵Daniel Sanders2017-03-071-16/+35
| | | | | | | | | | | | | | | | | | knows how to generate it. Summary: This will allow future patches to inspect the details of the LLT. The implementation is now split between the Support and CodeGen libraries to allow TableGen to use this class without introducing layering concerns. Thanks to Ahmed Bougacha for finding a reasonable way to avoid the layering issue and providing the version of this patch without that problem. Reviewers: t.p.northover, qcolombet, rovka, aditya_nandakumar, ab, javed.absar Subscribers: arsenm, nhaehnle, mgorny, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30046 llvm-svn: 297177
* [X86] Quick fix for build bot failure (r297127) due to unused variable.Ayman Musa2017-03-071-2/+1
| | | | llvm-svn: 297130
* [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX ↵Ayman Musa2017-03-074-0/+353
| | | | | | | | | | | | compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
* [TableGen] Ensure proper ordering of subtarget feature namesKrzysztof Parzyszek2017-03-061-4/+17
| | | | | | | Recommit r297039 without the testcase. The MIR testcase did not work well with MC code emitter. llvm-svn: 297080
* Revert r297039, it's causing some mysterious buildbot failuresKrzysztof Parzyszek2017-03-061-17/+4
| | | | llvm-svn: 297062
* [TableGen] Ensure proper ordering of subtarget feature namesKrzysztof Parzyszek2017-03-061-4/+17
| | | | llvm-svn: 297039
* Fixed IntOperandMatcher::emitCxxPredicateExpr argumentsSimon Pilgrim2017-02-241-1/+1
| | | | | | Extra const in the StringRef argument meant that MSVC complained about it not correctly overriding from OperandPredicateMatcher::emitCxxPredicateExpr (which didn't have the const) llvm-svn: 296138
* [globalisel] Decouple src pattern operands from dst pattern operands.Daniel Sanders2017-02-241-53/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
* Fix missing call to base class constructor in r296121.Daniel Sanders2017-02-241-1/+3
| | | | | | | The 'Kind' member used in RTTI for InstructionPredicateMatcher was not initialized but went undetected since I always ended up with the correct value. llvm-svn: 296126
* [globalisel] Sort RuleMatchers by priority.Daniel Sanders2017-02-241-2/+165
| | | | | | | | | | | | | | | | | | | | | | Summary: This makes more important rules have priority over less important rules. For example, '%a = G_ADD $b:s64, $c:s64' has priority over '%a = G_ADD $b:s32, $c:s32'. Previously these rules were emitted in the correct order by chance. NFC in this patch but it is required to make the next patch work correctly. Depends on D29710 Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka Reviewed By: ab, rovka Subscribers: javed.absar, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29711 llvm-svn: 296121
* tablegen: Fix android buildPavel Labath2017-02-211-1/+2
| | | | | | use llvm::to_string instead of std:: version. llvm-svn: 295711
* Add a wrapper around copy_if in STLExtras; NFCSanjoy Das2017-02-211-4/+3
| | | | | | I will add one more use for this in a later change. llvm-svn: 295685
* [globalisel] OperandPredicateMatcher's shouldn't need to generate the ↵Daniel Sanders2017-02-201-17/+18
| | | | | | | | | | | | | | | | | | | | | | | | MachineOperand expr. NFC Summary: Each OperandPredicateMatcher shouldn't need to know how to generate the expression to reference a MachineOperand. The OperandMatcher should provide it. In addition to separating responsibilities, this also lays some groundwork for decoupling source patterns from destination patterns to allow invented operands or operands provided by GlobalISel's equivalent to the ComplexPattern<> class. Depends on D29709 Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D29710 llvm-svn: 295668
* [globalisel] Separate the SelectionDAG importer from the emitter. NFCDaniel Sanders2017-02-201-5/+11
| | | | | | | | | | | | | | | | Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
* [X86][AVX] Extend hasVEX_WPrefix bit to accept WIG value (W Ignore) + update ↵Ayman Musa2017-02-202-11/+15
| | | | | | | | | | | all AVX instructions with the new value. Add WIG value to all of AVX instructions which ignore the W-bit in their encoding, instead of giving them the default value of 0. This patch is needed for a follow up work on EVEX2VEX pass (replacing EVEX encoded instructions with their corresponding VEX version when possible). Differential Revision: https://reviews.llvm.org/D29876 llvm-svn: 295643
* [TableGen] Make sure EnforceSameSize populates the type sets if necessary.Craig Topper2017-02-181-0/+6
| | | | | | This was found by another commit I'm working on. llvm-svn: 295578
* [Tablegen] Instrumenting table gen DAGGenISelDAGAditya Nandakumar2017-02-141-4/+135
| | | | | | | | | | To help assist in debugging ISEL or to prioritize GlobalISel backend work, this patch adds two more tables to <Target>GenISelDAGISel.inc - one which contains the patterns that are used during selection and the other containing include source location of the patterns Enabled through CMake varialbe LLVM_ENABLE_DAGISEL_COV llvm-svn: 295081
* [GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC.Ahmed Bougacha2017-02-101-55/+63
| | | | | | | | | | | | | | Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
* [TableGen][AsmWriterEmitter] Use a deterministic order to sort InstrAliasesQuentin Colombet2017-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Inside an alias group, when ordering instruction aliases, we rely on the priority field to sort them. When the priority is not set or more generally when there is a tie between two aliases, we used to rely on the lexicographic order. However, this order can change for the anonymous records when more instruction, intrinsic, etc. are inserted. For instance, given two anonymous records r1 and r2 with respective name A_999 and A_1000, their lexicography order will be r2 then r1. Now, if an instruction is added before them, their name will become respectively A_1000 and A_1001, thus the lexicography order will be r1 then r2, i.e., it changed. If that happens in an alias group, the assembly output would prefer a different alias for no apparent good reasons. A way to fix that is to use proper priority for all aliases, but we can also make the tie breaker comparison smarter and use a deterministic ordering. This is what this patch does. llvm-svn: 294695
* [GlobalISel] Simplify StringRef parameters. NFC.Ahmed Bougacha2017-02-091-9/+8
| | | | | | 'const' on StringRef parameters adds no guarantees. Remove it. llvm-svn: 294555
* Revert r294437 as it broke an asan buildbot.Amara Emerson2017-02-081-7/+2
| | | | llvm-svn: 294523
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-081-2/+7
| | | | | | | | | | | | | | | | | | | | | | | This patch checks the number of operands in the resulting instruction instead of just the alias, then skips over tied operands when generating the printing method. This allows us to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARMARM. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D29219 llvm-svn: 294437
* Move mnemonicIsValid to Mips target.Craig Topper2017-02-081-24/+0
| | | | | | | | | | | | | | | | | | | | Summary: The Mips target is the only user of mnemonicIsValid. This patch moves this method from AsmMatcherEmitter.cpp to MipsAsmParser.cpp, getting rid of the method in all other targets where it generated warnings about an unused function. Patch by Gonsolo. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: sdardis Differential Revision: https://reviews.llvm.org/D28748 llvm-svn: 294400
* [TableGen] Use less stack in DAGISelMatcherOptJon Chesterfield2017-02-061-9/+15
| | | | | | | | Refactor a helper function, FactorNodes, to search for a push node in constant space. This resolves a problem in a not-yet-upstreamed backend where a recursive pattern blew the call stack (at a depth of 255) under a debug build of tablegen. No functional change so no new test coverage. The change is minimal to avoid disturbing existing behaviour. Differential Revision: https://reviews.llvm.org/D29080 llvm-svn: 294230
* [GlobalISel] Add a few comments to the tablegen backend. NFC.Ahmed Bougacha2017-02-041-4/+14
| | | | | | Based on a review of D29478 by Kristof Beyls. llvm-svn: 294077
* [GlobalISel] Print the matched patterns using an action.Ahmed Bougacha2017-02-041-8/+16
| | | | | | | | This lets us split out PatternToMatch from the top-level RuleMatcher, where it doesn't really belong. That, in turn, lets us eventually generate RuleMatchers from non-SelectionDAG sources. llvm-svn: 294076
* [GlobalISel] Separate matchers with newlines in emitted selector. NFC.Ahmed Bougacha2017-02-041-4/+4
| | | | | | | We don't try very hard to format the emitted code, but newlines are an easy way to make it more readable. llvm-svn: 294074
* [globalisel] Fix missing break.Daniel Sanders2017-02-031-0/+1
| | | | | | The instruction selector has been emitting the register bank information too. llvm-svn: 294007
* [globalisel] Make the MatchAction hierarchy consistent with the matchers. NFC.Daniel Sanders2017-02-011-17/+27
| | | | | | | | | | Reviewers: aditya_nandakumar, rovka, t.p.northover, qcolombet, ab Subscribers: dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29321 llvm-svn: 293760
* TableGen: use fully qualified name for StringLiteralSaleem Abdulrasool2017-01-311-2/+2
| | | | | | | | | Use the qualified name for StringLiteral (llvm::StringLiteral) when generating the sources. This is needed as the generated files may be used out-of-tree (e.g. swift) where you may not have a `using namespace llvm;` resulting in an undefined lookup. llvm-svn: 293577
* Fix the GCC build.Benjamin Kramer2017-01-301-2/+2
| | | | | | This is fairly ugly, but apparently GCC still doesn't understand C++11. llvm-svn: 293535
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