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* [X86] Space out the encodings of X86 instruction formats. I plan to add some ↵Craig Topper2016-08-221-83/+83
| | | | | | | | new encodings in future commits and this will reduce the size of those commits. NFC This tries to keep all the ModRM memory and register forms in their own regions of the encodings. Hoping to make it simple on some of the switch statements that operate on these encodings. llvm-svn: 279422
* [X86] Merge small helper function into the switch that calls it since they ↵Craig Topper2016-08-221-17/+9
| | | | | | both operate on the same variable. NFC llvm-svn: 279421
* [X86] Explicitly list all X86 instruction forms in switch statement so its ↵Craig Topper2016-08-221-1/+10
| | | | | | easier to detect when one is missing. NFC llvm-svn: 279420
* AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . ↵Igor Breger2016-02-251-16/+20
| | | | | | | | Change memory operand parser handling. Differential Revision: http://reviews.llvm.org/D17564 llvm-svn: 261862
* [X86] Remove some unused encoding checks from the disassembler table building.Craig Topper2016-02-201-4/+0
| | | | llvm-svn: 261418
* [TableGen,X86] Add NDEBUG check to a variable initialization that's only ↵Craig Topper2016-02-181-0/+2
| | | | | | used by asserts. NFC llvm-svn: 261188
* [TableGen,X86] Remove extra optional operand from RawFrm. RawFrm with 2 ↵Craig Topper2016-02-181-3/+1
| | | | | | immediates is handled by RawFrmImm8/RawFrmImm16. llvm-svn: 261187
* [TableGen] Fix inconsistent spacing. NFCCraig Topper2016-02-161-2/+2
| | | | llvm-svn: 260935
* [TableGen] Stop passing by reference an integer that doesn't get modified. NFCCraig Topper2016-02-161-1/+1
| | | | llvm-svn: 260934
* [TableGen] Remove unused member variable. NFCCraig Topper2016-02-161-1/+0
| | | | llvm-svn: 260933
* [X86][PKU] Add {RD,WR}PKRU encodingAsaf Badouh2015-12-241-6/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D15711 llvm-svn: 256366
* [X86] Part 2 to fix x86-64 fp128 calling convention.Chih-Hung Hsieh2015-12-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | Part 1 was submitted in http://reviews.llvm.org/D15134. Changes in this part: * X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class. * X86CallingConv.td: Pass f128 values in XMM registers or on stack. * X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td: Add instruction selection patterns for f128. * X86ISelLowering.cpp: When target has MMX registers, configure MVT::f128 in FR128RegClass, with TypeSoftenFloat action, and custom actions for some opcodes. Add missed cases of MVT::f128 in places that handle f32, f64, or vector types. Add TODO comment to support f128 type in inline assembly code. * SelectionDAGBuilder.cpp: Fix infinite loop when f128 type can have VT == TLI.getTypeToTransformTo(Ctx, VT). * Add unit tests for x86-64 fp128 type. Differential Revision: http://reviews.llvm.org/D11438 llvm-svn: 255558
* AVX-512: Added all SKX forms of GATHER instructions.Elena Demikhovsky2015-06-281-0/+6
| | | | | | | Added intrinsics. Added encoding and tests. llvm-svn: 240905
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-091-0/+3
| | | | | | Added encoding tests. llvm-svn: 239403
* AVX-512: Added VPMOVx2M instructions for SKX,Elena Demikhovsky2015-04-211-0/+6
| | | | | | fixed encoding of VPMOVM2x. llvm-svn: 235385
* [X86] Add the remaining 11 possible exact ModRM formats. This makes their ↵Craig Topper2015-02-151-51/+62
| | | | | | encodings linear which can then be used to simplify some other code. llvm-svn: 229279
* [X86] Add support for parsing and printing the mnemonic aliases for the XOP ↵Craig Topper2015-02-131-0/+2
| | | | | | VPCOM instructions. llvm-svn: 229078
* [X86] Teach disassembler to handle illegal immediates on AVX512 integer ↵Craig Topper2015-01-281-0/+2
| | | | | | compare instructions. llvm-svn: 227302
* [X86] Replace i32i8imm on SSE/AVX instructions with i32u8imm which will make ↵Craig Topper2015-01-251-0/+3
| | | | | | the assembler bounds check them. It will also make them print as unsigned. llvm-svn: 227032
* [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.Craig Topper2015-01-211-0/+3
| | | | | | This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate. llvm-svn: 226645
* Replace size method call of containers to empty method where appropriateAlexander Kornienko2015-01-151-1/+1
| | | | | | | | | | | | | | | | This patch was generated by a clang tidy checker that is being open sourced. The documentation of that checker is the following: /// The emptiness of a container should be checked using the empty method /// instead of the size method. It is not guaranteed that size is a /// constant-time function, and it is generally more efficient and also shows /// clearer intent to use empty. Furthermore some containers may implement the /// empty method but not implement the size method. Using empty whenever /// possible makes it easier to switch to another container in the future. Patch by Gábor Horváth! llvm-svn: 226161
* [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the ↵Craig Topper2015-01-081-1/+2
| | | | | | LEA variants in Intel syntax. The memory operand is inherently unsized. llvm-svn: 225432
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-071-1/+0
| | | | llvm-svn: 225343
* [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.Craig Topper2015-01-061-2/+4
| | | | | | Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. llvm-svn: 225256
* [X86] Remove unused operand type from disassembler handling. NFCCraig Topper2015-01-051-1/+0
| | | | llvm-svn: 225151
* [X86] Disassembler support for move to/from %rax with a 32-bit memory offset ↵Craig Topper2015-01-031-0/+4
| | | | | | is REX.W and AdSize prefix are both present. llvm-svn: 225099
* [X86] Make the instructions that use AdSize16/32/64 co-exist together ↵Craig Topper2015-01-021-11/+30
| | | | | | | | | | without using mode predicates. This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used. Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction. llvm-svn: 225075
* [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit ↵Craig Topper2014-12-311-0/+4
| | | | | | modes with all 4 combinations of OpSize and AdSize prefixes being present or not. llvm-svn: 225036
* [X86] Remove the single AdSize indicator and replace it with separate ↵Craig Topper2014-12-241-3/+7
| | | | | | | | AdSize16/32/64 flags. This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler. llvm-svn: 224809
* [AVX512] Support mask register in MRMDestReg formatAdam Nemet2014-10-081-0/+2
| | | | | | This is necessary for masking vextract*x4. llvm-svn: 219359
* [X86 disasm tblegen backend] Clean up numPhysicalOperands assertsAdam Nemet2014-10-011-42/+35
| | | | | | | | | | | | | | No functionality change intended. This implements Elena's idea to put the new additionalOperand outside the switch to cover all cases (http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140929/237763.html). Note only nontrivial change is in MRMSrcMemFrm. This requires an inclusive interval of [2, 4] because we have prefix-dependent *optional* immediate operand. llvm-svn: 218790
* [x86] Fix a pretty horrible bug and inconsistency in the x86 asmChandler Carruth2014-09-061-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | parsing (and latent bug in the instruction definitions). This is effectively a revert of r136287 which tried to address a specific and narrow case of immediate operands failing to be accepted by x86 instructions with a pretty heavy hammer: it introduced a new kind of operand that behaved differently. All of that is removed with this commit, but the test cases are both preserved and enhanced. The core problem that r136287 and this commit are trying to handle is that gas accepts both of the following instructions: insertps $192, %xmm0, %xmm1 insertps $-64, %xmm0, %xmm1 These will encode to the same byte sequence, with the immediate occupying an 8-bit entry. The first form was fixed by r136287 but that broke the prior handling of the second form! =[ Ironically, we would still emit the second form in some cases and then be unable to re-assemble the output. The reason why the first instruction failed to be handled is because prior to r136287 the operands ere marked 'i32i8imm' which forces them to be sign-extenable. Clearly, that won't work for 192 in a single byte. However, making thim zero-extended or "unsigned" doesn't really address the core issue either because it breaks negative immediates. The correct fix is to make these operands 'i8imm' reflecting that they can be either signed or unsigned but must be 8-bit immediates. This patch backs out r136287 and then changes those places as well as some others to use 'i8imm' rather than one of the extended variants. Naturally, this broke something else. The custom DAG nodes had to be updated to have a much more accurate type constraint of an i8 node, and a bunch of Pat immediates needed to be specified as i8 values. The fallout didn't end there though. We also then ceased to be able to match the instruction-specific intrinsics to the instructions so modified. Digging, this is because they too used i32 rather than i8 in their signature. So I've also switched those intrinsics to i8 arguments in line with the instructions. In order to make the intrinsic adjustments of course, I also had to add auto upgrading for the intrinsics. I suspect that the intrinsic argument types may have led everything down this rabbit hole. Pretty happy with the result. llvm-svn: 217310
* [SKX] avx512_icmp_packed multiclass extensionRobert Khasanov2014-08-251-0/+2
| | | | | | | | | | | | | Extended avx512_icmp_packed multiclass by masking versions. Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions. Added corresponding _vl multiclasses. Added encoding tests for CPCMP{EQ|GT}* instructions. Add more fields for X86VectorVTInfo. Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions Differential Revision: http://reviews.llvm.org/D5024 llvm-svn: 216383
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-311-56/+59
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* [SKX] Enabling mask logic instructions: encoding, loweringRobert Khasanov2014-07-281-0/+2
| | | | | | | | Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ} Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 214081
* [SKX] Enabling mask instructions: encoding, loweringRobert Khasanov2014-07-231-0/+4
| | | | | | | | KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213757
* [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.Robert Khasanov2014-07-211-0/+14
| | | | | | | | | | | | Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-171-2/+15
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-1/+1
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* [x86] Simplify disassembler code slightly.Craig Topper2014-02-261-4/+4
| | | | llvm-svn: 202233
* [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. ↵Craig Topper2014-02-201-2/+1
| | | | | | Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. llvm-svn: 201767
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-191-47/+46
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Put some of the X86 formats in a more logical order.Craig Topper2014-02-191-20/+20
| | | | llvm-svn: 201645
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-7/+6
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Add an x86 prefix encoding for instructions that would decode to a different ↵Craig Topper2014-02-181-10/+38
| | | | | | instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. llvm-svn: 201538
* Remove filtering concept from X86 disassembler table generation. It's no ↵Craig Topper2014-02-131-47/+14
| | | | | | longer necessary. llvm-svn: 201299
* Remove special case filtering for instructions with lock prefix as they are ↵Craig Topper2014-02-121-6/+0
| | | | | | all marked with isCodeGenOnly already. llvm-svn: 201216
* Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear ↵Craig Topper2014-02-121-6/+0
| | | | | | from the disassembler table build without custom filtering code. llvm-svn: 201215
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-299/+40
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-40/+299
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
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