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path: root/llvm/utils/TableGen/X86RecognizableInstr.cpp
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* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-2/+65
| | | | llvm-svn: 191874
* AVX-512: Added masked SHIFT commands, more encoding testsElena Demikhovsky2013-08-221-17/+23
| | | | llvm-svn: 189005
* Remove use of sprintf added to X86 disassembler tablegen code. Send message ↵Craig Topper2013-07-281-4/+2
| | | | | | with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file. llvm-svn: 187333
* fixed compilation issueElena Demikhovsky2013-07-281-0/+1
| | | | llvm-svn: 187325
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-4/+156
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.Stefanus Du Toit2013-06-181-0/+6
| | | | | | | | For decoding, keep the current behavior of always decoding these as their REP versions. In the future, this could be improved to recognize the cases where these behave as XACQUIRE and XRELEASE and decode them as such. llvm-svn: 184207
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-17/+19
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-8/+9
| | | | llvm-svn: 177888
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-0/+11
| | | | | | rdar://13318048 llvm-svn: 176828
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-0/+1
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs llvm-svn: 174920
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-3/+1
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Add support of RTM from TSX extensionMichael Liao2012-11-081-8/+9
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-191-15/+1
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Add support for converting llvm.fma to fma4 instructions.Craig Topper2012-08-311-0/+2
| | | | llvm-svn: 162999
* Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The ↵Craig Topper2012-07-301-2/+1
| | | | | | isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. llvm-svn: 160951
* Remove some unnecessary filter checks. They were already covered by ↵Craig Topper2012-07-301-12/+0
| | | | | | IsCodeGenOnly llvm-svn: 160950
* Remove check for sub class of X86Inst from filter function since caller ↵Craig Topper2012-07-301-6/+2
| | | | | | guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already. llvm-svn: 160949
* Simplify code that filtered certain instructions in two different ways. No ↵Craig Topper2012-07-301-14/+1
| | | | | | functional change. llvm-svn: 160948
* Remove check for f256mem from has256BitOperands as nothing depended on it ↵Craig Topper2012-07-301-1/+1
| | | | | | and it isn't the only 256-bit memory type anyway. llvm-svn: 160946
* Remove trailing whitespace.Craig Topper2012-07-301-85/+85
| | | | llvm-svn: 160945
* Make l/q suffixes on AVX forms of scalar convert instructions consistent ↵Craig Topper2012-07-261-2/+1
| | | | | | with their non-AVX forms. llvm-svn: 160775
* Move around some enum elements so that lastMRM corrects gets assigned 56, whichRichard Trieu2012-07-181-2/+2
| | | | | | | is one more that MRM_DF which is 55. Previously, it held value 45, the same as MRM_D0. llvm-svn: 160465
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-4/+8
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-121-13/+13
| | | | | | myself and Manman Ren. llvm-svn: 160110
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+4
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer2012-05-291-2/+6
| | | | | | | | | | | extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+2
| | | | llvm-svn: 153935
* Fix the x86 disassembler to at least print the lock prefix if it is the firstKevin Enderby2012-03-091-3/+3
| | | | | | | prefix. Added a FIXME to remind us this still does not work when it is not the first prefix. llvm-svn: 152414
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-0/+5
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-191-8/+9
| | | | llvm-svn: 150899
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-181-1/+9
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-301-5/+9
| | | | llvm-svn: 147368
* Add FMA4 instructions to disassembler.Craig Topper2011-12-301-0/+7
| | | | llvm-svn: 147367
* Remove some unnecessary filtering checks from X86 disassembler table build.Craig Topper2011-11-191-35/+8
| | | | llvm-svn: 144986
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-3/+6
| | | | llvm-svn: 143895
* Add X86 RORX instructionCraig Topper2011-10-231-14/+23
| | | | llvm-svn: 142741
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-18/+27
| | | | llvm-svn: 142141
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-13/+9
| | | | llvm-svn: 142122
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper2011-10-161-4/+0
| | | | | | VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. llvm-svn: 142117
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-161-5/+18
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-151-8/+50
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-141-0/+2
| | | | llvm-svn: 141947
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-111-2/+8
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-061-0/+6
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. llvm-svn: 141274
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-4/+7
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper2011-10-011-0/+2
| | | | llvm-svn: 140955
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-011-6/+9
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-3/+8
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND ↵Craig Topper2011-09-141-5/+0
| | | | | | from being recognized by disassembler. llvm-svn: 139691
* Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper2011-09-131-3/+1
| | | | | | being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. llvm-svn: 139588
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