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* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-299/+40
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-40/+299
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* Simplify a bunch of code by removing the need for the x86 disassembler table ↵Craig Topper2014-02-101-301/+36
| | | | | | builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201060
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-101-0/+6
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-47/+46
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.Craig Topper2014-02-021-10/+10
| | | | llvm-svn: 200625
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-021-20/+23
| | | | | | in TSFlags. llvm-svn: 200624
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-311-121/+69
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-311-3/+2
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+5
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+12
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-221-0/+12
| | | | llvm-svn: 199803
* [x86] Fix disassembly of MOV16ao16 et al.David Woodhouse2014-01-201-2/+0
| | | | | | | | | | The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It also turns out to have been unnecessary. The disassembler handles the AdSize prefix for itself, and doesn't care about the difference between (e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and don't worry about it. llvm-svn: 199654
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-2/+30
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* Simplify x86 disassembler table handling of when to use ↵Craig Topper2014-01-151-22/+17
| | | | | | TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. llvm-svn: 199295
* Remove stray comma in enum to satisfy -Wpedantic.Craig Topper2014-01-141-1/+1
| | | | llvm-svn: 199194
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-17/+36
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-0/+2
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't ↵Craig Topper2014-01-061-7/+0
| | | | | | being used. llvm-svn: 198589
* Use patterns to remove some duplicate instructions.Craig Topper2014-01-051-3/+1
| | | | llvm-svn: 198550
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-051-2/+1
| | | | llvm-svn: 198547
* Remove no longer needed x86 disassembler hack.Craig Topper2014-01-051-6/+0
| | | | llvm-svn: 198546
* Mark x86 _alt instructions as AsmParserOnly so they will be omitted from ↵Craig Topper2014-01-051-2/+1
| | | | | | disassembler without string matches. llvm-svn: 198545
* Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode ↵Craig Topper2014-01-051-3/+1
| | | | | | and remove disassmbler table emitter hack. llvm-svn: 198544
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-051-1/+2
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. llvm-svn: 198543
* Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the ↵Craig Topper2014-01-051-3/+0
| | | | | | corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
* Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. ↵Craig Topper2014-01-041-2/+1
| | | | | | Remove disassembler hack. llvm-svn: 198515
* Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it ↵Craig Topper2014-01-041-2/+1
| | | | | | won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. llvm-svn: 198475
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-021-1/+0
| | | | llvm-svn: 198336
* Remove unused HasFROperands field from disassembler.Craig Topper2014-01-021-14/+0
| | | | llvm-svn: 198332
* Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack ↵Craig Topper2014-01-021-4/+0
| | | | | | from the disassembler table builder. llvm-svn: 198327
* Remove unnecessary stirng comparison from disassembler.Craig Topper2014-01-021-1/+0
| | | | llvm-svn: 198325
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-021-4/+0
| | | | | | table builder doesn't need to string match them to exclude them. llvm-svn: 198323
* Remove unused function argument.Craig Topper2014-01-021-2/+2
| | | | llvm-svn: 198291
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-011-2/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-011-8/+4
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-011-0/+2
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-011-29/+25
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-311-25/+29
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-301-29/+25
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* Remove EscapeFilter. It's funcionality can be covered by correctly using ↵Craig Topper2013-12-301-2/+15
| | | | | | ExtendedFilter and ExactFilter. No functional change. llvm-svn: 198226
* [x86] Rename In32BitMode predicate to Not64BitModeEric Christopher2013-12-201-2/+3
| | | | | | | | | | | That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse llvm-svn: 197768
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-161-0/+7
| | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-2/+5
| | | | | | added EVEX_KZ to tablegen llvm-svn: 193959
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-0/+3
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
* Remove more filters from the disassembler. Mark some AVX512 instructions as ↵Craig Topper2013-10-121-5/+0
| | | | | | CodeGenOnly. llvm-svn: 192525
* Mark some more instructions as CodeGenOnly. Remove filters from the ↵Craig Topper2013-10-121-4/+0
| | | | | | disassembler. llvm-svn: 192522
* Remove another unnecessary filter from the disassembler.Craig Topper2013-10-111-3/+0
| | | | llvm-svn: 192425
* Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.Craig Topper2013-10-101-1/+1
| | | | llvm-svn: 192339
* More x86 disassembler filtering cleanup.Craig Topper2013-10-091-4/+1
| | | | llvm-svn: 192279
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