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path: root/llvm/utils/TableGen/X86RecognizableInstr.cpp
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* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-4/+2
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Fixed a bug where the disassembler would allow an immediateSean Callanan2010-04-071-1/+1
| | | | | | | | | argument that had to be between 0 and 7 to have any value, firing an assert later in the AsmPrinter. Now, the disassembler rejects instructions with out-of-range values for that immediate. llvm-svn: 100694
* Check in tablegen changes to fix disassembler related failures caused by r98465.Evan Cheng2010-03-141-0/+1
| | | | llvm-svn: 98468
* Changed the table generator so that the X86Sean Callanan2010-02-241-3/+4
| | | | | | disassembler never recognizes InitReg instructions. llvm-svn: 97017
* Added the rdtscp instruction to the x86 instructionSean Callanan2010-02-131-1/+2
| | | | | | tables. llvm-svn: 96073
* Fixed encodings for invlpg, invept, and invvpid.Sean Callanan2010-02-131-32/+7
| | | | llvm-svn: 96065
* remove special cases for vmlaunch, vmresume, vmxoff, and swapgsChris Lattner2010-02-131-8/+8
| | | | | | fix swapgs to be spelled right. llvm-svn: 96058
* Remove special cases for [LM]FENCE, MONITOR and MWAIT fromChris Lattner2010-02-121-3/+0
| | | | | | encoder and decoder by using new MRM_ forms. llvm-svn: 96048
* Reworked the Intel disassembler to support instructionsSean Callanan2010-02-121-17/+51
| | | | | | | | | | | | whose opcodes extend into the ModR/M field using the Form field of the instruction rather than by special casing each instruction. Commented out the special casing of VMCALL, which is the first instruction to use this special form. While I was in the neighborhood, added a few comments for people modifying the Intel disassembler. llvm-svn: 96043
* add a bunch of mod/rm encoding types for fixed mod/rm bytes.Chris Lattner2010-02-121-2/+3
| | | | | | | This will work better for the disassembler for modeling things like lfence/monitor/vmcall etc. llvm-svn: 95960
* Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner2010-02-101-7/+4
| | | | | | | | | for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). llvm-svn: 95753
* Fixes to the X86 disassembler:Sean Callanan2009-12-221-3/+3
| | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
* Add missing newlines at EOF (for clang++).Daniel Dunbar2009-12-191-1/+1
| | | | llvm-svn: 91756
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-0/+959
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
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