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path: root/llvm/utils/TableGen/InstrInfoEmitter.cpp
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* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-071-6/+6
| | | | | | namespace. NFC llvm-svn: 307362
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-121-10/+14
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289475
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-1/+2
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-0/+1
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-1/+0
| | | | | | | hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-0/+1
| | | | | | | | | | | descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
* XRay: Add entry and exit sledsDean Michael Berris2016-07-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: In this patch we implement the following parts of XRay: - Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches. - Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts). - X86-specific nop sleds as described in the white paper. - A machine function pass that adds the different instrumentation marker instructions at a very late stage. - A way of identifying which return opcode is considered "normal" for each architecture. There are some caveats here: 1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet. 2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library. Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D19904 llvm-svn: 275367
* [TableGen] Use range-based for loop. NFCCraig Topper2016-02-161-2/+2
| | | | llvm-svn: 260928
* [TableGen] Don't call emitSourceFileHeader a second time in the middle of ↵Craig Topper2016-02-111-3/+1
| | | | | | the output file. llvm-svn: 260501
* [TableGen] Whitespace cleanup in output file. NFCCraig Topper2016-02-111-14/+14
| | | | llvm-svn: 260500
* [TableGen] Simplify code slightly. NFCCraig Topper2016-02-111-6/+3
| | | | llvm-svn: 260499
* [TableGen] Store result of getInstructionsByEnumValue in an ArrayRef instead ↵Craig Topper2016-02-011-6/+6
| | | | | | of accidentally copying to a vector. llvm-svn: 259336
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper2016-01-171-2/+2
| | | | | | to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-051-1/+1
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* [WinEH] Make FuncletLayout more robust against catchretDavid Majnemer2015-10-011-3/+3
| | | | | | | | | Catchret transfers control from a catch funclet to an earlier funclet. However, it is not completely clear which funclet the catchret target is part of. Make this clear by stapling the catchret target's funclet membership onto the CATCHRET SDAG node. llvm-svn: 249052
* Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor ↵Hans Wennborg2015-09-101-22/+20
| | | | | | | | | fixes" Except the changes that defined virtual destructors as =default, because that ran into problems with GCC 4.7 and overriding methods that weren't noexcept. llvm-svn: 247298
* Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"Hans Wennborg2015-09-101-20/+22
| | | | | | | This caused build breakges, e.g. http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/24926 llvm-svn: 247226
* Fix Clang-tidy misc-use-override warnings, other minor fixesHans Wennborg2015-09-101-22/+20
| | | | | | | | Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D12740 llvm-svn: 247216
* Add support for the convergent flag at the MC and MachineInstr levels.Owen Anderson2015-05-281-31/+32
| | | | llvm-svn: 238450
* Expand the Flags field of MCInstrDesc to 64 bits, while simultaneouslyOwen Anderson2015-05-281-2/+2
| | | | | | | | | | | shrinking the Size and NumDefs fields to offset the size growth, and reordering the fields to preserve a good packing. This is necessary in the short term for adding a convergent flag, and simultaneously future-proofs us against more flags being added in the future. llvm-svn: 238445
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-4/+4
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-4/+4
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-4/+4
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Fix tablegen's PrintFatalError function to run registered fileJames Y Knight2015-05-111-4/+2
| | | | | | | | | | | | | | | cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-4/+4
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-4/+4
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Use the variable names from the TargetInstrInfo source when weEric Christopher2015-03-131-5/+7
| | | | | | | reference them in the generated files. A few characters aren't huge here and CFSetupOpcode is much more readable than S0. llvm-svn: 232132
* Add a return after the llvm namespace code for a little extraEric Christopher2015-03-131-3/+3
| | | | | | readability in generated files. llvm-svn: 232131
* Fix a couple of depedent->dependent typos.Eric Christopher2015-02-261-1/+1
| | | | llvm-svn: 230584
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-4/+4
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-4/+4
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* Target: Allow target specific operand typesTom Stellard2015-01-121-1/+1
| | | | | | | | | | | | | | | | | | | This adds two new fields to the RegisterOperand TableGen class: string OperandNamespace = "MCOI"; string OperandType = "OPERAND_REGISTER"; These fields can be used to specify a target specific operand type, which will be stored in the OperandType member of the MCOperandInfo object. This can be useful for targets that need to store some extra information about operands that cannot be expressed using the target independent types. For example, in the R600 backend, there are operands which can take either registers or immediates and it is convenient to be able to specify this in the TableGen definitions. llvm-svn: 225661
* Tablegen output formatting fixes.Craig Topper2014-11-231-2/+4
| | | | llvm-svn: 222633
* Add isInsertSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
* Add isExtractSubreg property.Quentin Colombet2014-08-201-0/+1
| | | | | | | | | | | | | This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
* Add isRegSequence property.Quentin Colombet2014-08-111-0/+1
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* Make getNamedOperandIdx readonlyMatt Arsenault2014-08-011-0/+1
| | | | llvm-svn: 214524
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-301-5/+5
| | | | llvm-svn: 207611
* c++11: Tidy up tblgen w/ range loops.Jim Grosbach2014-04-181-62/+53
| | | | | | IntrInfoEmitter cleanup. llvm-svn: 206553
* Fix a vector that was passed by value instead of reference.Craig Topper2014-02-051-5/+5
| | | | llvm-svn: 200827
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-4/+6
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-6/+4
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.Ahmed Bougacha2013-11-171-0/+31
| | | | llvm-svn: 194978
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-4/+6
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+13
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* TableGen: Enumerate Schedule Model too.Vincent Lejeune2013-09-031-1/+9
| | | | llvm-svn: 189839
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-221-2/+2
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* Revert "TableGen: Enumerate Schedule Model too."Tom Stellard2013-07-311-7/+0
| | | | | | This reverts commit 2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0. llvm-svn: 187525
* TableGen: Enumerate Schedule Model too.Vincent Lejeune2013-07-311-0/+7
| | | | llvm-svn: 187511
* Teaching llvm-tblgen to not emit a switch statement when there are no case ↵Aaron Ballman2013-07-151-23/+30
| | | | | | statements. llvm-svn: 186330
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