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author | Quentin Colombet <qcolombet@apple.com> | 2014-08-11 22:17:14 +0000 |
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committer | Quentin Colombet <qcolombet@apple.com> | 2014-08-11 22:17:14 +0000 |
commit | d533cdf26f9a602b1f45734ebbc6169faee5dcdd (patch) | |
tree | 7bc4c4e5145da4f0ab0382e5a03db7173ac4960a /llvm/utils/TableGen/InstrInfoEmitter.cpp | |
parent | 35f986d3cd6942cff0fc7f78062924ebebd6988d (diff) | |
download | bcm5719-llvm-d533cdf26f9a602b1f45734ebbc6169faee5dcdd.tar.gz bcm5719-llvm-d533cdf26f9a602b1f45734ebbc6169faee5dcdd.zip |
Add isRegSequence property.
This patch adds a new property: isRegSequence and the related target hooks:
TargetIntrInfo::getRegSequenceInputs and
TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific
instruction is a (kind of) REG_SEQUENCE.
<rdar://problem/12702965>
llvm-svn: 215394
Diffstat (limited to 'llvm/utils/TableGen/InstrInfoEmitter.cpp')
-rw-r--r-- | llvm/utils/TableGen/InstrInfoEmitter.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index e625394b8e8..edd2f1f0e3c 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -505,6 +505,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)"; if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)"; + if (Inst.isRegSequence) OS << "|(1<<MCID::RegSequence)"; // Emit all of the target-specific flags... BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); |