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path: root/llvm/utils/TableGen/DAGISelMatcherGen.cpp
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [TableGen] Preserve order of output operands in DAGISelMatcherGenCraig Topper2018-12-051-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes support in DAGISelMatcher backend for DAG nodes with multiple result values. Previously the order of results in selected DAG nodes always matched the order of results in ISel patterns. After the change the order of results matches the order of operands in OutOperandList instead. For example, given this definition from the attached test case: def INSTR : Instruction { let OutOperandList = (outs GPR:$r1, GPR:$r0); let InOperandList = (ins GPR:$t0, GPR:$t1); let Pattern = [(set i32:$r0, i32:$r1, (udivrem i32:$t0, i32:$t1))]; } the DAGISelMatcher backend currently produces a matcher that creates INSTR nodes with the first result `$r0` and the second result `$r1`, contrary to the order in the OutOperandList. The order of operands in OutOperandList does not matter at all, which is unexpected (and unfortunate) because the order of results of a DAG node does matters, perhaps a lot. With this change, if the order in OutOperandList does not match the order in Pattern, DAGISelMatcherGen emits CompleteMatch opcodes with the order of results taken from OutOperandList. Backend writers can use it to express result reorderings in TableGen. If the order in OutOperandList matches the order in Pattern, the result of DAGISelMatcherGen is unaffected. Patch by Eugene Sharygin Reviewers: andreadb, bjope, hfinkel, RKSimon, craig.topper Reviewed By: craig.topper Subscribers: nhaehnle, craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D55055 llvm-svn: 348326
* TableGen/ISel: Allow PatFrag predicate code to access captured operandsNicolai Haehnle2018-11-301-18/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This simplifies writing predicates for pattern fragments that are automatically re-associated or commuted. For example, a followup patch adds patterns for fragments of the form (add (shl $x, $y), $z) to the AMDGPU backend. Such patterns are automatically commuted to (add $z, (shl $x, $y)), which makes it basically impossible to refer to $x, $y, and $z generically in the PredicateCode. With this change, the PredicateCode can refer to $x, $y, and $z simply as `Operands[i]`. Test confirmed that there are no changes to any of the generated files when building all (non-experimental) targets. Change-Id: I61c00ace7eed42c1d4edc4c5351174b56b77a79c Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D51994 llvm-svn: 347992
* [TableGen] Return ValueTypeByHwMode by const reference from ↵Simon Pilgrim2018-08-161-3/+3
| | | | | | | | CodeGenRegisterClass::getValueTypeNum Avoids costly std::map copies inside ValueTypeByHwMode constructor llvm-svn: 339884
* [TableGen] Support multi-alternative pattern fragmentsUlrich Weigand2018-07-131-45/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A TableGen instruction record usually contains a DAG pattern that will describe the SelectionDAG operation that can be implemented by this instruction. However, there will be cases where several different DAG patterns can all be implemented by the same instruction. The way to represent this today is to write additional patterns in the Pattern (or usually Pat) class that map those extra DAG patterns to the instruction. This usually also works fine. However, I've noticed cases where the current setup seems to require quite a bit of extra (and duplicated) text in the target .td files. For example, in the SystemZ back-end, there are quite a number of instructions that can implement an "add-with-overflow" operation. The same instructions also need to be used to implement just plain addition (simply ignoring the extra overflow output). The current solution requires creating extra Pat pattern for every instruction, duplicating the information about which particular add operands map best to which particular instruction. This patch enhances TableGen to support a new PatFrags class, which can be used to encapsulate multiple alternative patterns that may all match to the same instruction. It operates the same way as the existing PatFrag class, except that it accepts a list of DAG patterns to match instead of just a single one. As an example, we can now define a PatFrags to match either an "add-with-overflow" or a regular add operation: def z_sadd : PatFrags<(ops node:$src1, node:$src2), [(z_saddo node:$src1, node:$src2), (add node:$src1, node:$src2)]>; and then use this in the add instruction pattern: defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; These SystemZ target changes are implemented here as well. Note that PatFrag is now defined as a subclass of PatFrags, which means that some users of internals of PatFrag need to be updated. (E.g. instead of using PatFrag.Fragment you now need to use !head(PatFrag.Fragments).) The implementation is based on the following main ideas: - InlinePatternFragments may now replace each original pattern with several result patterns, not just one. - parseInstructionPattern delays calling InlinePatternFragments and InferAllTypes. Instead, it extracts a single DAG match pattern from the main instruction pattern. - Processing of the DAG match pattern part of the main instruction pattern now shares most code with processing match patterns from the Pattern class. - Direct use of main instruction patterns in InferFromPattern and EmitResultInstructionAsOperand is removed; everything now operates solely on DAG match patterns. Reviewed by: hfinkel Differential Revision: https://reviews.llvm.org/D48545 llvm-svn: 336999
* [TableGen] Fix some bad formatting. NFCCraig Topper2018-07-111-4/+4
| | | | llvm-svn: 336751
* Revert r334764, as it breaks some botsFlorian Hahn2018-06-141-115/+115
| | | | llvm-svn: 334767
* [TableGen] Make TreePatternNode::getChild return a reference (NFC)Florian Hahn2018-06-141-115/+115
| | | | | | | | The return value of TreePatternNode::getChild is never null. This patch also updates various places that use return values of getChild to also use references. Those changes were suggested post-commit for D47463. llvm-svn: 334764
* [TableGen] Avoid leaking TreePatternNodes by using shared_ptr.Florian Hahn2018-05-301-9/+6
| | | | | | | | | | | | By using std::shared_ptr for TreePatternNode, we can avoid leaking them. Reviewers: craig.topper, dsanders, stoklund, tstellar, zturner Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47463 llvm-svn: 333591
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-19/+31
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* NFC: spell correction.Lama Saba2017-07-301-1/+1
| | | | | | | | On behalf of jbhateja Differential Revision: https://reviews.llvm.org/D35885 llvm-svn: 309521
* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-071-1/+1
| | | | | | namespace. NFC llvm-svn: 307362
* Use range for loops. NFCI.Simon Pilgrim2017-06-191-4/+2
| | | | llvm-svn: 305693
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-4/+4
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Apply most suggestions of clang-tidy's performance-unnecessary-value-paramBenjamin Kramer2016-06-081-2/+2
| | | | | | | Avoids unnecessary copies. All changes audited & pass tests with asan. No functional change intended. llvm-svn: 272190
* SDAG: Remove OPC_MarkGlueResults and associated logic. NFCJustin Bogner2016-05-051-11/+0
| | | | | | | | | This opcode never happens in practice, and yet the logic we have in place to handle it would be undefined behaviour if we ever executed it. Remove it rather than trying to refactor code that's never reached. llvm-svn: 268692
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* Fix tablegen's PrintFatalError function to run registered fileJames Y Knight2015-05-111-2/+4
| | | | | | | | | | | | | | | cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
* [TableGen] Use 'isa' to identify UnsetInits rather than comparing with the ↵Craig Topper2015-04-221-1/+1
| | | | | | singleton object created by UnsetInit::get(). Makes it more consistent with the other types. llvm-svn: 235465
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-4/+4
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-6/+4
| | | | | | range-for isn't suitable. llvm-svn: 223260
* Support REG_SEQUENCE in tablegen.Matt Arsenault2014-11-021-9/+24
| | | | | | | | | The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. llvm-svn: 221117
* Fix typoMatt Arsenault2014-11-021-1/+1
| | | | llvm-svn: 221116
* TableGen: permit non-leaf ComplexPattern usesTim Northover2014-05-201-41/+71
| | | | | | | | | | | | | | | | | | This allows the results of a ComplexPattern check to be distributed to separate named Operands, instead of the current system where all results must apply (and match perfectly) with a single Operand. For example, if "some_addrmode" is a ComplexPattern producing two results, you can write: def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)), (INST GPR64:$base, imm:$offset)>; This should allow neater instruction definitions in TableGen that don't put all possible aspects of addressing into a single operand, but are still usable with relatively simple C++ CodeGen idioms. llvm-svn: 209206
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-8/+8
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* Fix typo in commment tyep->type.Craig Topper2014-01-251-1/+1
| | | | llvm-svn: 200089
* Use ArrayRef to simplify some code.Craig Topper2014-01-211-7/+4
| | | | llvm-svn: 199712
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-241-0/+6
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. llvm-svn: 177844
* Allow direct value types in pattern definitions.Jakob Stoklund Olesen2013-03-231-3/+11
| | | | | | | | | | | | | | | | | Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. llvm-svn: 177828
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-191-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. llvm-svn: 177428
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-10/+6
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-5/+5
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-061-2/+1
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. llvm-svn: 163315
* Teach TableGen to put chains on more instructionsTim Northover2012-06-261-0/+7
| | | | | | | | | | | When generating selection tables for Pat instances, TableGen relied on an output Instruction's Pattern field being set to infer whether a chain should be added. This patch adds additional logic to check various flag fields so that correct code can be generated even if Pattern is unset. llvm-svn: 159217
* fix a failure path to print the right thing, part of PR12357Chris Lattner2012-03-261-1/+1
| | | | llvm-svn: 153457
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-2/+2
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Unconstify InitsDavid Greene2011-07-291-6/+6
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-6/+6
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-7/+6
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-6/+7
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Add support for alternative register names, useful for instructions whose ↵Owen Anderson2011-06-271-7/+11
| | | | | | | | operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-181-12/+3
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-2/+2
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather thanCameron Zwarich2011-05-191-14/+48
| | | | | | | the root if there is only one such node. This leaves only 2 verifier failures in the entire test suite when running "make check". llvm-svn: 131677
* Teach TableGen to pre-calculate register enum values when creating theJim Grosbach2011-03-111-1/+14
| | | | | | | | | | | CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 llvm-svn: 127456
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-8/+8
| | | | llvm-svn: 122513
* continue renaming flag -> glue.Chris Lattner2010-12-231-31/+31
| | | | llvm-svn: 122506
* Tidy up a bit. Trailing whitespace, hard tabs and 80-columns.Jim Grosbach2010-12-211-97/+97
| | | | llvm-svn: 122337
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