summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/DAGISelMatcherGen.cpp
diff options
context:
space:
mode:
authorDavid Blaikie <dblaikie@gmail.com>2014-12-03 19:58:41 +0000
committerDavid Blaikie <dblaikie@gmail.com>2014-12-03 19:58:41 +0000
commitc0bb5cab0fb46f3ea12c09c9f062016e9b36ab63 (patch)
treed184052fab70892ef3d6340d767bcb3d9f074791 /llvm/utils/TableGen/DAGISelMatcherGen.cpp
parent38303a329f9334ad961351724bdd38c2c80d4157 (diff)
downloadbcm5719-llvm-c0bb5cab0fb46f3ea12c09c9f062016e9b36ab63.tar.gz
bcm5719-llvm-c0bb5cab0fb46f3ea12c09c9f062016e9b36ab63.zip
Range-for some stuff related to RegClasses, and comment cases where range-for isn't suitable.
llvm-svn: 223260
Diffstat (limited to 'llvm/utils/TableGen/DAGISelMatcherGen.cpp')
-rw-r--r--llvm/utils/TableGen/DAGISelMatcherGen.cpp10
1 files changed, 4 insertions, 6 deletions
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index 4a73b003598..47d3b647156 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -27,21 +27,19 @@ static MVT::SimpleValueType getRegisterValueType(Record *R,
bool FoundRC = false;
MVT::SimpleValueType VT = MVT::Other;
const CodeGenRegister *Reg = T.getRegBank().getReg(R);
- ArrayRef<CodeGenRegisterClass*> RCs = T.getRegBank().getRegClasses();
- for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = *RCs[rc];
- if (!RC.contains(Reg))
+ for (const auto *RC : T.getRegBank().getRegClasses()) {
+ if (!RC->contains(Reg))
continue;
if (!FoundRC) {
FoundRC = true;
- VT = RC.getValueTypeNum(0);
+ VT = RC->getValueTypeNum(0);
continue;
}
// If this occurs in multiple register classes, they all have to agree.
- assert(VT == RC.getValueTypeNum(0));
+ assert(VT == RC->getValueTypeNum(0));
}
return VT;
}
OpenPOWER on IntegriCloud