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path: root/llvm/utils/TableGen/DAGISelMatcherGen.cpp
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* Fix tablegen's PrintFatalError function to run registered fileJames Y Knight2015-05-111-2/+4
| | | | | | | | | | | | | | | cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
* [TableGen] Use 'isa' to identify UnsetInits rather than comparing with the ↵Craig Topper2015-04-221-1/+1
| | | | | | singleton object created by UnsetInit::get(). Makes it more consistent with the other types. llvm-svn: 235465
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-4/+4
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-6/+4
| | | | | | range-for isn't suitable. llvm-svn: 223260
* Support REG_SEQUENCE in tablegen.Matt Arsenault2014-11-021-9/+24
| | | | | | | | | The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. llvm-svn: 221117
* Fix typoMatt Arsenault2014-11-021-1/+1
| | | | llvm-svn: 221116
* TableGen: permit non-leaf ComplexPattern usesTim Northover2014-05-201-41/+71
| | | | | | | | | | | | | | | | | | This allows the results of a ComplexPattern check to be distributed to separate named Operands, instead of the current system where all results must apply (and match perfectly) with a single Operand. For example, if "some_addrmode" is a ComplexPattern producing two results, you can write: def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)), (INST GPR64:$base, imm:$offset)>; This should allow neater instruction definitions in TableGen that don't put all possible aspects of addressing into a single operand, but are still usable with relatively simple C++ CodeGen idioms. llvm-svn: 209206
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-8/+8
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* Fix typo in commment tyep->type.Craig Topper2014-01-251-1/+1
| | | | llvm-svn: 200089
* Use ArrayRef to simplify some code.Craig Topper2014-01-211-7/+4
| | | | llvm-svn: 199712
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-241-0/+6
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. llvm-svn: 177844
* Allow direct value types in pattern definitions.Jakob Stoklund Olesen2013-03-231-3/+11
| | | | | | | | | | | | | | | | | Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. llvm-svn: 177828
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-191-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. llvm-svn: 177428
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-10/+6
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-5/+5
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-061-2/+1
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. llvm-svn: 163315
* Teach TableGen to put chains on more instructionsTim Northover2012-06-261-0/+7
| | | | | | | | | | | When generating selection tables for Pat instances, TableGen relied on an output Instruction's Pattern field being set to infer whether a chain should be added. This patch adds additional logic to check various flag fields so that correct code can be generated even if Pattern is unset. llvm-svn: 159217
* fix a failure path to print the right thing, part of PR12357Chris Lattner2012-03-261-1/+1
| | | | llvm-svn: 153457
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-2/+2
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Unconstify InitsDavid Greene2011-07-291-6/+6
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-6/+6
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-7/+6
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-6/+7
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Add support for alternative register names, useful for instructions whose ↵Owen Anderson2011-06-271-7/+11
| | | | | | | | operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-181-12/+3
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-2/+2
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather thanCameron Zwarich2011-05-191-14/+48
| | | | | | | the root if there is only one such node. This leaves only 2 verifier failures in the entire test suite when running "make check". llvm-svn: 131677
* Teach TableGen to pre-calculate register enum values when creating theJim Grosbach2011-03-111-1/+14
| | | | | | | | | | | CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 llvm-svn: 127456
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-8/+8
| | | | llvm-svn: 122513
* continue renaming flag -> glue.Chris Lattner2010-12-231-31/+31
| | | | llvm-svn: 122506
* Tidy up a bit. Trailing whitespace, hard tabs and 80-columns.Jim Grosbach2010-12-211-97/+97
| | | | llvm-svn: 122337
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-2/+2
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* zap dead code.Chris Lattner2010-09-041-1/+0
| | | | llvm-svn: 113071
* We already have this as OperandNode.Eric Christopher2010-08-101-5/+2
| | | | llvm-svn: 110748
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-241-0/+9
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. llvm-svn: 104492
* fix a long standing fixme, which required fixing a bunch of otherChris Lattner2010-03-271-25/+27
| | | | | | | | | | | | | issues to get here. We now trim the result type list of the CompleteMatch or MorphNodeTo operation to be the same size as the thing we're matching. this means that if you match (add GPR, GPR) with an instruction that produces a normal result and a flag that we now trim the result in tblgen instead of having to do it dynamically. This exposed a bunch of inconsistencies in result counting that happened to be getting lucky since the days of the old isel. llvm-svn: 99728
* hoist some funky logic into CodeGenInstructionChris Lattner2010-03-271-2/+1
| | | | | | | | | from two places in CodeGenDAGPatterns.cpp, and use it in DAGISelMatcherGen.cpp instead of using an incorrect predicate that happened to get lucky on our current targets. llvm-svn: 99726
* continue pushing tblgen's support for nodes with multipleChris Lattner2010-03-271-8/+17
| | | | | | | | results forward. We can now handle an instruction that produces one implicit def and one result instead of one or the other when not at the root of the pattern. llvm-svn: 99725
* add plumbing for handling multiple result nodes Chris Lattner2010-03-241-10/+9
| | | | | | in some more places. llvm-svn: 99366
* major surgery on tblgen: generalize TreePatternNodeChris Lattner2010-03-191-10/+15
| | | | | | | | | to maintain a list of types (one for each result of the node) instead of a single type. There are liberal hacks added to emulate the old behavior in various situations, but they can start disolving now. llvm-svn: 98999
* resolve fixme: we now infer the instruction-level 'isvariadic' bitChris Lattner2010-03-191-5/+5
| | | | | | from the pattern if present, and we use it instead of the bit. llvm-svn: 98938
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-1/+2
| | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
* look up instructions by record, not by name.Chris Lattner2010-03-191-1/+1
| | | | llvm-svn: 98904
* expand tblgen's support for instructions with implicit defs.Chris Lattner2010-03-181-6/+14
| | | | llvm-svn: 98900
* Completely rewrite tblgen's type inference mechanism,Chris Lattner2010-03-151-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! llvm-svn: 98534
* more factoring.Chris Lattner2010-03-071-10/+4
| | | | llvm-svn: 97911
* zap fixme.Chris Lattner2010-03-041-4/+0
| | | | llvm-svn: 97705
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