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path: root/llvm/utils/TableGen/DAGISelEmitter.cpp
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* For instructions which produce no result, e.g. store, chain's Resno == 0.Evan Cheng2005-12-101-4/+6
| | | | llvm-svn: 24652
* Add a new SDTCisPtrTy constraint, which indicates that an operand must haveChris Lattner2005-12-091-0/+6
| | | | | | the same type as the pointer type for a target. llvm-svn: 24649
* * Do not allow nodes which produce chain results (e.g. loads) to be folded ifEvan Cheng2005-12-091-407/+414
| | | | | | | | | it has more than one real use (non-chain uses). * Record folded chain producing node in CodeGenMap. * Do not fold a chain producing node if it has already been selected as an operand of a chain use. llvm-svn: 24647
* Prevent folding of instructions which produce chains that have more than 1 ↵Evan Cheng2005-12-091-3/+8
| | | | | | real use llvm-svn: 24643
* * Make sure complex pattern operands are selected first since their selectEvan Cheng2005-12-091-60/+76
| | | | | | | functions can return false and causing the instruction pattern match to fail. * Code clean up. llvm-svn: 24642
* * Added an explicit type field to ComplexPattern.Evan Cheng2005-12-081-3/+2
| | | | | | * Renamed MatchingNodes to RootNodes. llvm-svn: 24636
* Added support for ComplexPattern. These are patterns that require C++ patternEvan Cheng2005-12-081-38/+127
| | | | | | | matching code that is not currently auto-generated by tblgen, e.g. X86 addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4. llvm-svn: 24634
* * Infer instruction property hasCtrlDep from pattern if it has one.Evan Cheng2005-12-051-31/+50
| | | | | | * Fixed a bug related to hasCtrlDep property use. llvm-svn: 24610
* Implement PR673: for explicit register references, use type informationChris Lattner2005-12-051-15/+8
| | | | | | if available llvm-svn: 24597
* Generate code to silence bogus GCC warnings.Chris Lattner2005-12-051-1/+1
| | | | llvm-svn: 24593
* * Commit the fix (by Chris) for a tblgen type inferencing bug.Evan Cheng2005-12-041-66/+191
| | | | | | | | | | | * Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. llvm-svn: 24587
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-6/+10
| | | | | | work. This change has no effect on generated code. llvm-svn: 24563
* Teach tblgen to accept register source operands in patterns, e.g.Evan Cheng2005-12-011-7/+65
| | | | | | | | | | | def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), "shl{b} {%cl, $dst|$dst, %CL}", [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>; This generates a CopyToReg operand and added its 2nd result to the shl as a flag operand. llvm-svn: 24557
* Stop checking the ValueType of the CodeGenInstruction. Instead, use theNate Begeman2005-12-011-15/+40
| | | | | | | ValueType from the RegisterClass or Operands. This step is necessary to allow RegisterClasses to have multiple ValueTypes. llvm-svn: 24555
* Make the code generated by tblgen return the result of SelectNodeTo, toChris Lattner2005-11-301-2/+1
| | | | | | permit future changes. llvm-svn: 24553
* Better error message when unrecognized opcode is seen.Evan Cheng2005-11-291-1/+6
| | | | llvm-svn: 24519
* Validate that the input to 'Pat' patterns is sane.Chris Lattner2005-11-171-0/+8
| | | | llvm-svn: 24393
* teach tblgen to be smart enough to handle tglobaladdr nodesChris Lattner2005-11-171-0/+2
| | | | llvm-svn: 24391
* fix a tblgen bug that Evan ran into, where we would lose the '$src' nameChris Lattner2005-11-161-4/+4
| | | | | | on patterns like "(set R32:$dst, (i32 imm:$src))" llvm-svn: 24383
* Reject integer literals that are out of range for their type.Chris Lattner2005-11-031-1/+19
| | | | llvm-svn: 24162
* Add support for immediates directly in the pattern, this allows itanium toChris Lattner2005-11-021-3/+31
| | | | | | | | define: def : Pat<(i1 1), (CMPEQ r0, r0)>; llvm-svn: 24149
* Make negative immediates in patterns work correctly, silence some warningsChris Lattner2005-10-291-1/+1
| | | | | | building the itanium backend. llvm-svn: 24095
* Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accuratelyChris Lattner2005-10-281-3/+4
| | | | | | | reflect what it is. Convert some more code over to use it. llvm-svn: 24072
* Use the new interface Jim addedChris Lattner2005-10-281-15/+7
| | | | llvm-svn: 24071
* Condcodes are in the ISD namespaceChris Lattner2005-10-261-1/+1
| | | | llvm-svn: 24010
* Add support for CondCode'sChris Lattner2005-10-261-4/+14
| | | | llvm-svn: 24008
* Emit some boilerplate for targetsChris Lattner2005-10-251-0/+29
| | | | llvm-svn: 23983
* Make tblgen emit:Chris Lattner2005-10-211-8/+16
| | | | | | | tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern! for a bad pattern, instead of an ugly assertion. llvm-svn: 23854
* add support for literal immediates in patterns to match, allowing us toChris Lattner2005-10-191-9/+21
| | | | | | | | | | write things like this: def : Pat<(add GPRC:$in, 12), (ADD12 GPRC:$in)>; Andrew: if this isn't enough or doesn't work for you, please lemme know. llvm-svn: 23819
* Add basic support for integer constants in pattern results.Chris Lattner2005-10-191-0/+14
| | | | llvm-svn: 23817
* Add support for patterns that have physical registers in them. Testcase:Chris Lattner2005-10-191-0/+12
| | | | | | | | | def : Pat<(trunc G8RC:$in), (OR8To4 G8RC:$in, X0)>; Even though this doesn't make any sense on PPC :) llvm-svn: 23815
* Asserting here is to violentChris Lattner2005-10-191-1/+3
| | | | llvm-svn: 23814
* Nate wants to define 'Pat's which turn into instructions that don't haveChris Lattner2005-10-191-4/+30
| | | | | | patterns. Certainly a logical request. llvm-svn: 23810
* Duraid pointed out that it is impolite to emit PPC:: into the IA64 backendChris Lattner2005-10-181-1/+5
| | | | llvm-svn: 23780
* Make the generated code significantly more memory efficient, by usingChris Lattner2005-10-161-13/+36
| | | | | | SelectNodeTo instead of getTargetNode when possible. llvm-svn: 23758
* Implement the last major missing piece in the DAG isel generator: when emittingChris Lattner2005-10-151-17/+47
| | | | | | | | a pattern match, make sure to emit the (minimal number of) type checks that verify the pattern matches this specific instruction. This allows FMA32 patterns to not match double expressions for example. llvm-svn: 23748
* Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOpChris Lattner2005-10-141-2/+41
| | | | | | | | type constraint. This lets tblgen realize that it doesn't need any dynamic type checks for fextend/fround on PPC (and many other targets), because there are only two fp types. llvm-svn: 23730
* Fairly serious rework of the typing code to add new int/fp lattice values.Chris Lattner2005-10-141-52/+84
| | | | | | Overall, no functionality change yet though. llvm-svn: 23729
* simplify the code a bitChris Lattner2005-10-141-26/+18
| | | | llvm-svn: 23728
* Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraintChris Lattner2005-10-141-0/+8
| | | | llvm-svn: 23725
* Implement a couple of new (important) features.Chris Lattner2005-10-141-48/+125
| | | | | | | | | | | | 1. If an operation has to be int or fp and the target only supports one int or fp type, relize that the op has to have that type. 2. If a target has operations on multiple types, do not emit matching code for patterns involving those operators, since we do not emit the code to check for them yet. This prevents PPC from generating FP ops currently. Also move some code around into more logical places. llvm-svn: 23724
* Teach tablegen to reassociate operators when possible. This allows it toChris Lattner2005-09-291-10/+96
| | | | | | find all of teh pattern matches for EQV from one definition llvm-svn: 23529
* Teach tblgen to build permutations of instructions, so that the target authorChris Lattner2005-09-291-6/+187
| | | | | | | | | | | doesn't have to specify them manually. It currently handles associativity, e.g. knowing that (X*Y)+Z also matches X+(Y*Z) and will be extended in the future. It is smart enough to not introduce duplicate patterns or patterns that can never match. llvm-svn: 23526
* add support for an associative markerChris Lattner2005-09-281-2/+4
| | | | llvm-svn: 23502
* Emit an error if instructions or patterns are defined but can never match.Chris Lattner2005-09-281-3/+47
| | | | | | | | | | | | | | Currently we check that immediate values live on the RHS of commutative operators. Defining ORI like this, for example: def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), "ori $dst, $src1, $src2", [(set GPRC:$dst, (or immZExt16:$src2, GPRC:$src1))]>; results in: tblgen: In ORI: Instruction can never match: Immediate values must be on the RHS of commutative operators! llvm-svn: 23501
* collect commutativity informationChris Lattner2005-09-281-0/+16
| | | | llvm-svn: 23499
* Prefer cheaper patterns to more expensive ones. Print the costs to the ↵Chris Lattner2005-09-281-39/+50
| | | | | | | | generated file llvm-svn: 23492
* Select Constant nodes to TargetConstant nodesChris Lattner2005-09-281-5/+19
| | | | llvm-svn: 23488
* memoize the assert resultsChris Lattner2005-09-261-2/+5
| | | | llvm-svn: 23457
* Emit the switch stmt cases in alphabetical order instead of pointer order,Chris Lattner2005-09-261-4/+19
| | | | | | which is not stable. llvm-svn: 23456
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