| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove trailing whitespace | Misha Brukman | 2005-04-22 | 1 | -5/+5 |
| | | | | | llvm-svn: 21428 | ||||
| * | Refactor code for numbering instructions into CodeGenTarget. | Chris Lattner | 2005-01-22 | 1 | -0/+16 |
| | | | | | llvm-svn: 19758 | ||||
| * | Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. | Chris Lattner | 2005-01-02 | 1 | -0/+2 |
| | | | | | llvm-svn: 19243 | ||||
| * | * Add option to read isLittleEndianEncoding for InstrInfo classes | Misha Brukman | 2004-10-14 | 1 | -0/+9 |
| | | | | | | | * Doxygen-ify some function comments llvm-svn: 16974 | ||||
| * | Add initial support for variants. This just parses the new format, no | Chris Lattner | 2004-10-03 | 1 | -1/+12 |
| | | | | | | | functionality is added llvm-svn: 16636 | ||||
| * | Add support for the isLoad and isStore flags, needed by the instruction ↵ | Nate Begeman | 2004-09-28 | 1 | -0/+2 |
| | | | | | | | scheduler llvm-svn: 16554 | ||||
| * | Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG | Chris Lattner | 2004-09-28 | 1 | -0/+1 |
| | | | | | llvm-svn: 16553 | ||||
| * | Alignment is now in bits. | Chris Lattner | 2004-08-21 | 1 | -2/+1 |
| | | | | | llvm-svn: 15976 | ||||
| * | Make alignment be in bits, just like size is | Chris Lattner | 2004-08-21 | 1 | -1/+2 |
| | | | | | llvm-svn: 15969 | ||||
| * | Support "Methods" in register classes in CodgeGenRegisterClass | Chris Lattner | 2004-08-21 | 1 | -0/+6 |
| | | | | | llvm-svn: 15965 | ||||
| * | Start parsing register classes into a more structured form | Chris Lattner | 2004-08-21 | 1 | -0/+32 |
| | | | | | llvm-svn: 15961 | ||||
| * | Read in declared reg sizes | Chris Lattner | 2004-08-21 | 1 | -0/+5 |
| | | | | | llvm-svn: 15960 | ||||
| * | Use CodeGenRegister class to make reading in of register information more | Chris Lattner | 2004-08-16 | 1 | -1/+14 |
| | | | | | | | systematic. llvm-svn: 15805 | ||||
| * | Make the AsmWriter a first-class tblgen object. Allow targets to specify | Chris Lattner | 2004-08-14 | 1 | -4/+17 |
| | | | | | | | name of the generated asmwriter class, and the name of the format string. llvm-svn: 15747 | ||||
| * | Start parsing more information from the Operand information | Chris Lattner | 2004-08-11 | 1 | -3/+10 |
| | | | | | llvm-svn: 15644 | ||||
| * | Remove special case hacks | Chris Lattner | 2004-08-11 | 1 | -8/+2 |
| | | | | | llvm-svn: 15643 | ||||
| * | Parse the operand list of the instruction. We currently support register ↵ | Chris Lattner | 2004-08-01 | 1 | -5/+36 |
| | | | | | | | and immediate operands. llvm-svn: 15390 | ||||
| * | Initial cut at an asm writer emitter. So far, this only handles emission of | Chris Lattner | 2004-08-01 | 1 | -2/+11 |
| | | | | | | | instructions, and only instructions that take no operands at that! llvm-svn: 15386 | ||||
| * | Add, and start using, the CodeGenInstruction class. This class represents | Chris Lattner | 2004-08-01 | 1 | -0/+36 |
| | | | | | | | an instance of the Instruction tablegen class. llvm-svn: 15385 | ||||
| * | Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h) | Chris Lattner | 2004-08-01 | 1 | -0/+99 |
| llvm-svn: 15382 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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