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| author | Nate Begeman <natebegeman@mac.com> | 2004-09-28 21:01:45 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2004-09-28 21:01:45 +0000 |
| commit | 996ddbc98e83f967412f467f6624943efc527a4d (patch) | |
| tree | de1d019b16742b090c10aaaac305418baf08aa90 /llvm/utils/TableGen/CodeGenTarget.cpp | |
| parent | 9b0dfa3c0d9244128075e0abd1693e1c33492aed (diff) | |
| download | bcm5719-llvm-996ddbc98e83f967412f467f6624943efc527a4d.tar.gz bcm5719-llvm-996ddbc98e83f967412f467f6624943efc527a4d.zip | |
Add support for the isLoad and isStore flags, needed by the instruction scheduler
llvm-svn: 16554
Diffstat (limited to 'llvm/utils/TableGen/CodeGenTarget.cpp')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenTarget.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp index ba214051cde..f7225f081d0 100644 --- a/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/CodeGenTarget.cpp @@ -195,6 +195,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) isBranch = R->getValueAsBit("isBranch"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); + isLoad = R->getValueAsBit("isLoad"); + isStore = R->getValueAsBit("isStore"); isTwoAddress = R->getValueAsBit("isTwoAddress"); isTerminator = R->getValueAsBit("isTerminator"); hasDelaySlot = R->getValueAsBit("hasDelaySlot"); |
