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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-11/+28
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Adding a v8i64 512-bit vector type. This will be used to model ARM NEON ↵Evan Cheng2010-05-131-0/+1
| | | | | | intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. llvm-svn: 103746
* Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng2010-05-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 llvm-svn: 102815
* fix CodeGenTarget::getRegisterVTs to not return the Chris Lattner2010-03-271-0/+5
| | | | | | | | same vt multiple times for a register. For example, ECX is in 5 different i32 reg classes, just return 1 i32 instead of 5. llvm-svn: 99727
* reject void in intrinsic type lists.Chris Lattner2010-03-231-7/+12
| | | | llvm-svn: 99347
* Change intrinsic result type for void to store it as an empty listChris Lattner2010-03-221-3/+6
| | | | | | | instead of as a single element list with VoidTy. Now with a fix for the verifier. llvm-svn: 99206
* Revert r99009 temporarily it seems to be breaking the bots.Eric Christopher2010-03-191-6/+3
| | | | llvm-svn: 99011
* Change intrinsic result type for void to store it as an empty listChris Lattner2010-03-191-3/+6
| | | | | | instead of as a single element list with VoidTy. llvm-svn: 99009
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-0/+2
| | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
* Finally change the instruction looking map to be a densemap fromChris Lattner2010-03-191-16/+29
| | | | | | | | | record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). llvm-svn: 98916
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-23/+24
| | | | | | Use CodeGenTarget::getInstNamespace in one place and fix it. llvm-svn: 98915
* revert 98912Chris Lattner2010-03-191-15/+15
| | | | llvm-svn: 98914
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-15/+15
| | | | llvm-svn: 98912
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-17/+14
| | | | | | | to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
* factor copy and paste code.Chris Lattner2010-03-191-53/+27
| | | | llvm-svn: 98908
* look up instructions by record, not by name.Chris Lattner2010-03-191-0/+6
| | | | llvm-svn: 98904
* Completely rewrite tblgen's type inference mechanism,Chris Lattner2010-03-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! llvm-svn: 98534
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-5/+5
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen2010-01-151-8/+1
| | | | | | Also, DEBUG_VALUE has side effects. llvm-svn: 93498
* Add DEBUG_DECLARE. Not used yet.Dale Johannesen2010-01-091-1/+8
| | | | llvm-svn: 93040
* Add DEBUG_VALUE. Not used yet.Dale Johannesen2010-01-081-1/+8
| | | | llvm-svn: 93030
* Remove the CPAttrParentAsRoot code, which is unused, and inconvenientDan Gohman2010-01-041-12/+0
| | | | | | for a refactoring I'm working on. llvm-svn: 92503
* Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen2009-09-281-5/+5
| | | | | | | | | | unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. llvm-svn: 83006
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-54/+54
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Fix a few more places in TableGen that need to handle EVT::vAny types.Bob Wilson2009-08-111-2/+4
| | | | llvm-svn: 78643
* Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsicBob Wilson2009-08-111-2/+3
| | | | | | arguments that are vectors of any size and element type. llvm-svn: 78631
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-56/+56
| | | | | | own struct type. llvm-svn: 78610
* Match X86 register names to number.Daniel Dunbar2009-07-291-0/+13
| | | | llvm-svn: 77404
* Remove the v3i32 and v3f32 value types: they are notDuncan Sands2009-07-151-2/+0
| | | | | | native for any supported targets. llvm-svn: 75785
* Revert 75308.Bob Wilson2009-07-141-17/+2
| | | | llvm-svn: 75565
* Add new vector types for 192-bit, 348-bit and 512-bit sizes.Bob Wilson2009-07-101-2/+17
| | | | | | | These are needed to represent ARM Neon struct datatypes containing 2, 3 or 4 separate vectors. llvm-svn: 75308
* Refactor TableGen's llvm::getName to share code with llvm::getEnumName,Bob Wilson2009-07-101-41/+4
| | | | | | since names are the same for almost all the types. llvm-svn: 75302
* Add new ValueType for metadata.Devang Patel2009-07-061-0/+1
| | | | llvm-svn: 74882
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-5/+4
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Add more vector ValueTypes for AVX and other extended vector instructionDavid Greene2009-06-291-8/+20
| | | | | | sets. llvm-svn: 74427
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-7/+0
| | | | llvm-svn: 72712
* Make the implicit inputs and outputs of target-independentDale Johannesen2009-06-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. llvm-svn: 72707
* Fix PR3994: LLVMMatchType arguments do not refer to absolute return valueBob Wilson2009-04-161-8/+18
| | | | | | | | | | and argument positions but only to the overloaded intrinsic parameters. Keep a separate list of these overloaded parameters in CodeGenTarget.cpp so they can be resolved easily. Remove assertions from IntrinsicEmitter.cpp: they were harmless but confusing, and the assertions elsewhere in TableGen will catch any incorrect values. llvm-svn: 69316
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-5/+5
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-2/+9
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Reapply 63765. Patches for clang and llvm-gcc to follow.Dale Johannesen2009-02-051-3/+7
| | | | llvm-svn: 63812
* Reverting 63765. This broke the build of both clangDale Johannesen2009-02-041-7/+3
| | | | | | and llvm-gcc. llvm-svn: 63786
* New feature: add support for target intrinsics being defined in theNate Begeman2009-02-041-3/+7
| | | | | | | | | target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. llvm-svn: 63765
* add nocapture attribute to llvm.mem* intrinsics and have tblgenChris Lattner2009-01-121-1/+4
| | | | | | parse them. tblgen doesn't yet do anything with this info though. llvm-svn: 62065
* Improve support for type-generic vector intrinsics by teaching TableGen howBob Wilson2009-01-071-2/+26
| | | | | | | | to handle LLVMMatchType intrinsic parameters, and by adding new subclasses of LLVMMatchType to match vector types with integral elements that are either twice as wide or half as wide as the elements of the matched type. llvm-svn: 61834
* Added support for vector widening.Mon P Wang2008-12-181-0/+6
| | | | llvm-svn: 61209
* Modify the intrinsics pattern to separate out the "return" types from theBill Wendling2008-11-131-16/+29
| | | | | | | | | | "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; llvm-svn: 59237
* Factor the code for determining the target-specific instructionDan Gohman2008-08-201-0/+15
| | | | | | namespace out of the isel emitters and into common code. llvm-svn: 55079
* Fix the string for MVT::isVoid.Dan Gohman2008-08-201-1/+1
| | | | llvm-svn: 55034
* Added support for overloading intrinsics (atomics) based on pointersMon P Wang2008-07-301-1/+3
| | | | | | | to different address spaces. This alters the naming scheme for those intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32 llvm-svn: 54195
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