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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAGEvan Cheng2005-12-231-0/+2
* Support for read / write from explicit registers with FlagVT type.Evan Cheng2005-12-171-0/+2
* * Added an explicit type field to ComplexPattern.Evan Cheng2005-12-081-3/+5
* Added support for ComplexPattern. These are patterns that require C++ patternEvan Cheng2005-12-081-0/+9
* * Commit the fix (by Chris) for a tblgen type inferencing bug.Evan Cheng2005-12-041-0/+1
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-8/+20
* Nuke CodeGenInstruction's ValueType member, it is no longer used.Nate Begeman2005-12-011-9/+4
* Add the new vector types to tablegenNate Begeman2005-11-291-0/+12
* Initialize this variable on all paths, fixing a crasher in windows. ThanksChris Lattner2005-11-191-1/+1
* Teach tblgen about instruction operands that have multiple MachineInstrChris Lattner2005-11-191-1/+4
* Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accuratelyChris Lattner2005-10-281-20/+8
* Do not let getLegalValueTypes return a list with duplicates in itChris Lattner2005-10-141-0/+7
* force all instruction operands to be named.Chris Lattner2005-09-141-2/+5
* Check that operands have unique names. REJECT instructions with broken operandChris Lattner2005-09-141-29/+39
* Add a new Record::getValueAsCode method to mirror the other getValueAs*Chris Lattner2005-09-131-11/+2
* Compute the value types that are natively supported by a target.Chris Lattner2005-09-081-0/+6
* spell this rightChris Lattner2005-08-261-1/+1
* spell this variable rightChris Lattner2005-08-261-1/+1
* Expose a new flag to TargetInstrInfoChris Lattner2005-08-261-0/+1
* Split register class "Methods" into MethodProtos and MethodBodiesChris Lattner2005-08-191-4/+10
* Read the namespace field from register classesChris Lattner2005-08-191-0/+7
* Fix a problem jeffc noticedChris Lattner2005-08-191-0/+1
* Figure out how many operands each instruction has, keep track of whetherChris Lattner2005-08-181-4/+7
* Remove trailing whitespaceMisha Brukman2005-04-221-5/+5
* Refactor code for numbering instructions into CodeGenTarget.Chris Lattner2005-01-221-0/+16
* Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.Chris Lattner2005-01-021-0/+2
* * Add option to read isLittleEndianEncoding for InstrInfo classesMisha Brukman2004-10-141-0/+9
* Add initial support for variants. This just parses the new format, noChris Lattner2004-10-031-1/+12
* Add support for the isLoad and isStore flags, needed by the instruction sched...Nate Begeman2004-09-281-0/+2
* Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAGChris Lattner2004-09-281-0/+1
* Alignment is now in bits.Chris Lattner2004-08-211-2/+1
* Make alignment be in bits, just like size isChris Lattner2004-08-211-1/+2
* Support "Methods" in register classes in CodgeGenRegisterClassChris Lattner2004-08-211-0/+6
* Start parsing register classes into a more structured formChris Lattner2004-08-211-0/+32
* Read in declared reg sizesChris Lattner2004-08-211-0/+5
* Use CodeGenRegister class to make reading in of register information moreChris Lattner2004-08-161-1/+14
* Make the AsmWriter a first-class tblgen object. Allow targets to specifyChris Lattner2004-08-141-4/+17
* Start parsing more information from the Operand informationChris Lattner2004-08-111-3/+10
* Remove special case hacksChris Lattner2004-08-111-8/+2
* Parse the operand list of the instruction. We currently support register and...Chris Lattner2004-08-011-5/+36
* Initial cut at an asm writer emitter. So far, this only handles emission ofChris Lattner2004-08-011-2/+11
* Add, and start using, the CodeGenInstruction class. This class representsChris Lattner2004-08-011-0/+36
* Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)Chris Lattner2004-08-011-0/+99
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