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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag andEvan Cheng2006-01-091-2/+0
| | | | | | | | | SNDPOutFlag to DAG nodes. These properties do not belong to target specific instructions. * Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's optional. Used by ret / call, etc. llvm-svn: 25154
* Added field noResults to Instruction.Evan Cheng2005-12-261-0/+1
| | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. llvm-svn: 25017
* * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAGEvan Cheng2005-12-231-0/+2
| | | | | | | support which is fragile. * Fixed a number of bugs. llvm-svn: 24996
* Support for read / write from explicit registers with FlagVT type.Evan Cheng2005-12-171-0/+2
| | | | llvm-svn: 24753
* * Added an explicit type field to ComplexPattern.Evan Cheng2005-12-081-3/+5
| | | | | | * Renamed MatchingNodes to RootNodes. llvm-svn: 24636
* Added support for ComplexPattern. These are patterns that require C++ patternEvan Cheng2005-12-081-0/+9
| | | | | | | matching code that is not currently auto-generated by tblgen, e.g. X86 addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4. llvm-svn: 24634
* * Commit the fix (by Chris) for a tblgen type inferencing bug.Evan Cheng2005-12-041-0/+1
| | | | | | | | | | | * Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. llvm-svn: 24587
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-8/+20
| | | | | | work. This change has no effect on generated code. llvm-svn: 24563
* Nuke CodeGenInstruction's ValueType member, it is no longer used.Nate Begeman2005-12-011-9/+4
| | | | llvm-svn: 24556
* Add the new vector types to tablegenNate Begeman2005-11-291-0/+12
| | | | llvm-svn: 24514
* Initialize this variable on all paths, fixing a crasher in windows. ThanksChris Lattner2005-11-191-1/+1
| | | | | | to JeffC for pointing this out. llvm-svn: 24426
* Teach tblgen about instruction operands that have multiple MachineInstrChris Lattner2005-11-191-1/+4
| | | | | | | operands, digging into them to find register values (used on X86). Patch by Evan Cheng! llvm-svn: 24424
* Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accuratelyChris Lattner2005-10-281-20/+8
| | | | | | | reflect what it is. Convert some more code over to use it. llvm-svn: 24072
* Do not let getLegalValueTypes return a list with duplicates in itChris Lattner2005-10-141-0/+7
| | | | llvm-svn: 23723
* force all instruction operands to be named.Chris Lattner2005-09-141-2/+5
| | | | llvm-svn: 23358
* Check that operands have unique names. REJECT instructions with broken operandChris Lattner2005-09-141-29/+39
| | | | | | lists: only don't parse them if they are entirely missing (sparcv9). llvm-svn: 23355
* Add a new Record::getValueAsCode method to mirror the other getValueAs*Chris Lattner2005-09-131-11/+2
| | | | | | methods. Use it to simplify some code. llvm-svn: 23336
* Compute the value types that are natively supported by a target.Chris Lattner2005-09-081-0/+6
| | | | llvm-svn: 23282
* spell this rightChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23099
* spell this variable rightChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23095
* Expose a new flag to TargetInstrInfoChris Lattner2005-08-261-0/+1
| | | | llvm-svn: 23094
* Split register class "Methods" into MethodProtos and MethodBodiesChris Lattner2005-08-191-4/+10
| | | | llvm-svn: 22928
* Read the namespace field from register classesChris Lattner2005-08-191-0/+7
| | | | llvm-svn: 22918
* Fix a problem jeffc noticedChris Lattner2005-08-191-0/+1
| | | | llvm-svn: 22903
* Figure out how many operands each instruction has, keep track of whetherChris Lattner2005-08-181-4/+7
| | | | | | or not it's variable. llvm-svn: 22885
* Remove trailing whitespaceMisha Brukman2005-04-221-5/+5
| | | | llvm-svn: 21428
* Refactor code for numbering instructions into CodeGenTarget.Chris Lattner2005-01-221-0/+16
| | | | llvm-svn: 19758
* Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.Chris Lattner2005-01-021-0/+2
| | | | llvm-svn: 19243
* * Add option to read isLittleEndianEncoding for InstrInfo classesMisha Brukman2004-10-141-0/+9
| | | | | | * Doxygen-ify some function comments llvm-svn: 16974
* Add initial support for variants. This just parses the new format, noChris Lattner2004-10-031-1/+12
| | | | | | functionality is added llvm-svn: 16636
* Add support for the isLoad and isStore flags, needed by the instruction ↵Nate Begeman2004-09-281-0/+2
| | | | | | scheduler llvm-svn: 16554
* Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAGChris Lattner2004-09-281-0/+1
| | | | llvm-svn: 16553
* Alignment is now in bits.Chris Lattner2004-08-211-2/+1
| | | | llvm-svn: 15976
* Make alignment be in bits, just like size isChris Lattner2004-08-211-1/+2
| | | | llvm-svn: 15969
* Support "Methods" in register classes in CodgeGenRegisterClassChris Lattner2004-08-211-0/+6
| | | | llvm-svn: 15965
* Start parsing register classes into a more structured formChris Lattner2004-08-211-0/+32
| | | | llvm-svn: 15961
* Read in declared reg sizesChris Lattner2004-08-211-0/+5
| | | | llvm-svn: 15960
* Use CodeGenRegister class to make reading in of register information moreChris Lattner2004-08-161-1/+14
| | | | | | systematic. llvm-svn: 15805
* Make the AsmWriter a first-class tblgen object. Allow targets to specifyChris Lattner2004-08-141-4/+17
| | | | | | name of the generated asmwriter class, and the name of the format string. llvm-svn: 15747
* Start parsing more information from the Operand informationChris Lattner2004-08-111-3/+10
| | | | llvm-svn: 15644
* Remove special case hacksChris Lattner2004-08-111-8/+2
| | | | llvm-svn: 15643
* Parse the operand list of the instruction. We currently support register ↵Chris Lattner2004-08-011-5/+36
| | | | | | and immediate operands. llvm-svn: 15390
* Initial cut at an asm writer emitter. So far, this only handles emission ofChris Lattner2004-08-011-2/+11
| | | | | | instructions, and only instructions that take no operands at that! llvm-svn: 15386
* Add, and start using, the CodeGenInstruction class. This class representsChris Lattner2004-08-011-0/+36
| | | | | | an instance of the Instruction tablegen class. llvm-svn: 15385
* Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)Chris Lattner2004-08-011-0/+99
llvm-svn: 15382
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