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path: root/llvm/utils/TableGen/CodeGenSchedule.cpp
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* [MiSched|TableGen] : Tidy up and modernise. NFC.Javed Absar2017-09-131-103/+89
| | | | | | | | | Replacing with range-based loop and substituting 'using'. Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D37748 llvm-svn: 313140
* [TableGen] Improve Debug Output for --debug-only=subtarget-emitter NFCIJoel Jones2017-06-281-0/+7
| | | | | | | | | Add headers for each section of output, with white space and "+++" to improve readability. Differential Revision: https://reviews.llvm.org/D34713 llvm-svn: 306492
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-311-1/+1
| | | | | | instead of a std::string. llvm-svn: 304347
* Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2016-11-301-16/+27
| | | | | | This preparation to remove SetVector.h dependency on SmallSet.h. llvm-svn: 288256
* Fix per-processor model scheduler definition completeness checkUlrich Weigand2016-10-311-1/+2
| | | | | | | | | | | | | | | The CodeGenSchedModels::checkCompleteness routine in TableGen/ CodeGenSchedule.cpp is supposed to verify for each processor model that is marked as "complete" that it actually defines a scheduling class for each instruction. However, this did not work correctly due to an incorrect check whether a scheduling class has an itinerary. Reviewer: atrick Differential revision: https://reviews.llvm.org/D26156 llvm-svn: 285622
* Improve tablegen gen-subtarget diagnostics for missing machine models.Andrew Trick2016-10-181-5/+8
| | | | | | | | | | | | -debug-only=subtarget-emitter prints a lot of machine model diagnostics. This prunes the output so that the "No machine model for XXX on processor YYY" only appears when there is definitely no machine model for that opcode. Previously it was printing that error even if the opcode was covered by a more general scheduling class. <rdar://problem/15919845> [TableGen][CodeGenSchedule] Debug output does not help spotting the missing scheduling classes llvm-svn: 284452
* Use the range variant of find/find_if instead of unpacking begin/endDavid Majnemer2016-08-121-10/+4
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278469
* Use the range variant of find_if instead of unpacking begin/endDavid Majnemer2016-08-121-5/+3
| | | | | | No functionality change is intended. llvm-svn: 278443
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-8/+5
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* Revert "Revert "[misched] Extend scheduler to handle unsupported features""Simon Dardis2016-06-241-1/+29
| | | | | | | | This reverts commit r273565. This was an over-eager revert. llvm-svn: 273658
* Revert "[misched] Extend scheduler to handle unsupported features"Simon Dardis2016-06-231-29/+1
| | | | | | | | This reverts commit r273551. Patch contained a wrong check for isUnsupported. llvm-svn: 273565
* [misched] Extend scheduler to handle unsupported featuresSimon Dardis2016-06-231-1/+29
| | | | | | | | | | | | | | | | | | | | | | | Currently isComplete = 1 requires that every instruction must be described, declared unsupported or marked as having no scheduling information for a processor. For some backends such as MIPS, this requirement entails long regex lists of instructions that are unsupported. This patch teaches Tablegen to skip over instructions that are associated with unsupported feature when checking if the scheduling model is complete. Patch by: Daniel Sanders Contributions by: Simon Dardis Reviewers: MatzeB Differential Reviewer: http://reviews.llvm.org/D20522 llvm-svn: 273551
* TableGen/CodeGenSchedule: Move some getAllDerivedDefinitions() calls out of ↵Matthias Braun2016-06-211-3/+8
| | | | | | | | | inner loops This cuts the runtime of the two slowest tblgen invocations in aarch64 in half for me... llvm-svn: 273235
* TableGen: Accept itinerary data when checking for schedmodel completenessMatthias Braun2016-03-031-4/+4
| | | | llvm-svn: 262548
* TableGen: Display helpfull message for incomplete models.Matthias Braun2016-03-011-1/+7
| | | | llvm-svn: 262399
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-011-0/+45
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* TableGen: Add hasNoSchedulingInfo to instructionsMatthias Braun2016-03-011-1/+2
| | | | | | | | | | | | | This introduces a new flag that indicates that a specific instruction will never be present when the MachineScheduler runs and therefore needs no scheduling information. This is in preparation for an upcoming commit which checks completeness of a scheduling model when tablegen runs. Differential Revision: http://reviews.llvm.org/D17728 llvm-svn: 262383
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper2016-01-171-4/+4
| | | | | | to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
* [TblGen] ArrayRefize CodeGenSchedule. No functionality change intended.Benjamin Kramer2015-10-241-50/+41
| | | | llvm-svn: 251187
* Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer2015-05-291-9/+6
| | | | | | | | | | | | | | | | | | | | If the type isn't trivially moveable emplace can skip a potentially expensive move. It also saves a couple of characters. Call sites were found with the ASTMatcher + some semi-automated cleanup. memberCallExpr( argumentCountIs(1), callee(methodDecl(hasName("push_back"))), on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))), hasArgument(0, bindTemporaryExpr( hasType(recordDecl(hasNonTrivialDestructor())), has(constructExpr()))), unless(isInTemplateInstantiation())) No functional change intended. llvm-svn: 238602
* [TableGen] Don't leak Expanders and Operators in SetTheory.Craig Topper2015-04-241-2/+2
| | | | llvm-svn: 235697
* Use range-based for loops. NFC.Craig Topper2014-12-091-26/+18
| | | | llvm-svn: 223762
* Update SetVector to rely on the underlying set's insert to return a ↵David Blaikie2014-11-191-2/+2
| | | | | | | | | | | | | pair<iterator, bool> This is to be consistent with StringSet and ultimately with the standard library's associative container insert function. This lead to updating SmallSet::insert to return pair<iterator, bool>, and then to update SmallPtrSet::insert to return pair<iterator, bool>, and then to update all the existing users of those functions... llvm-svn: 222334
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
* Use Regex objects by value (rather than 'new'ed) in CodeGenSchedule.David Blaikie2014-04-211-6/+4
| | | | llvm-svn: 206800
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-3/+3
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* Fix a false error reported by the tblgen backend for machine modelAndrew Trick2014-03-131-0/+12
| | | | | | | | | "ProcResource def is not included in the ProcResources". Some of the machine model definitions were not added to the processor's list used for diagnostics and error checking. llvm-svn: 203749
* [C++11] Add 'override' keywords to tablegen code.Craig Topper2014-03-051-3/+3
| | | | llvm-svn: 202937
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* [weak vtables] Place class definitions into anonymous namespaces to prevent ↵Juergen Ributzka2013-11-191-37/+31
| | | | | | | | | | weak vtables. This patch places class definitions in implementation files into anonymous namespaces to prevent weak vtables. This eliminates the need of providing an out-of-line definition to pin the vtable explicitly to the file. llvm-svn: 195092
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-30/+38
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-36/+30
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-30/+36
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-1/+1
| | | | | | size. llvm-svn: 186274
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-151-0/+13
| | | | | | And add Sandybridge/Haswell resource buffers. llvm-svn: 184034
* tblgen: Assert that InstRWs doesn't grows when we don't expect it.Benjamin Kramer2013-06-101-0/+1
| | | | llvm-svn: 183690
* tblgen: always lookup values from the original vector as it could be grown ↵Benjamin Kramer2013-06-091-6/+6
| | | | | | | | under our feet. PR16281. llvm-svn: 183630
* CodeGenSchedule: Use resize instead of copying a vectorArnold Schwaighofer2013-06-071-2/+2
| | | | llvm-svn: 183465
* CodeGenSchedule: smallvector.push_back(smallvector[0]) is dangerousArnold Schwaighofer2013-06-061-1/+3
| | | | | | | | | | The element passed to push_back is not copied before the vector reallocates. The client needs to copy the element first before passing it to push_back. No test case, will be tested by follow-up swift scheduler model change (it segfaults without this change). llvm-svn: 183459
* Fix a tblgen subtargetemitter bug, for future Swift support.Andrew Trick2013-06-051-4/+23
| | | | | | | | | | This fixes some of the ridiculously complex code for optimizing the machine model tables that are shared among all processors of a given target. A9 and Swift both use the "special" feature that maps old itinerary classes to new machine model defs. They map different overlapping subsets of instructions, which wasn't handled correctly. llvm-svn: 183302
* Machine model: verify well-formed processor resource groups.Andrew Trick2013-04-231-0/+51
| | | | llvm-svn: 180161
* Fix TableGen subtarget-emitter to handle A9/Swift.Andrew Trick2013-03-291-5/+11
| | | | | | | | A9 uses itinerary classes, Swift uses RW lists. This tripped some verification when we're expanding variants. I had to refine the verification a bit. llvm-svn: 178357
* Revert r178166. According to Howard, this code is actually ok.Dan Gohman2013-03-291-3/+1
| | | | llvm-svn: 178319
* Avoid undefined behavior from passing a std::vector's own contentsDan Gohman2013-03-271-1/+3
| | | | | | in as an argument to push_back. llvm-svn: 178166
* TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2013-03-261-1/+8
| | | | | | Allow variants to be defined only for some processors on a target. llvm-svn: 178074
* TableGen fix for the new machine model.Andrew Trick2013-03-181-4/+6
| | | | | | | | Properly handle cases where a group of instructions have different SchedRW lists with the same itinerary class. This was supposed to work, but I left in an early break. llvm-svn: 177317
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-161-123/+111
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
* Add SchedRW as an Instruction field.Jakob Stoklund Olesen2013-03-151-6/+6
| | | | | | | | | | | | | Don't require instructions to inherit Sched<...>. Sometimes it is more convenient to say: let SchedRW = ... in { ... } Which is now possible. llvm-svn: 177199
* MachineModel: Add a ProcResGroup class.Andrew Trick2013-03-141-0/+17
| | | | | | | | | | | | | | | | | This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; llvm-svn: 177112
* MachineModel: Inconsequential TableGen SubtargetEmitter fix.Andrew Trick2013-02-011-1/+15
| | | | | | | | Drive by fix. I noticed some missing logic that might bite future users. This shouldn't affect the final output on currently modeled targets. llvm-svn: 174142
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