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path: root/llvm/utils/TableGen/CodeGenRegisters.cpp
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* GlobalISel: Support physical register inputs in patternsMatt Arsenault2019-09-061-0/+15
* Retire llvm::less/equal in favor of C++14 std::less<>/equal_to<>.Benjamin Kramer2019-08-221-8/+10
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-151-2/+2
* [AMDGPU] Allow register tuples to set asm namesStanislav Mekhanoshin2019-07-191-3/+12
* Use llvm::stable_sortFangrui Song2019-04-231-2/+1
* [tablegen] Add locations to many PrintFatalError() callsDaniel Sanders2019-02-121-2/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [TableGen] Examine entire subreg compositions to detect ambiguityKrzysztof Parzyszek2018-11-291-5/+59
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-271-7/+7
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-07-021-3/+9
* [tablegen] Improve performance on *GenRegisterInfo.inc by replacing SparseVec...Daniel Sanders2018-06-081-3/+3
* [TableGen] Fix leaking synthesized registers.Florian Hahn2018-05-291-2/+12
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-46/+43
* [TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-061-11/+11
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-03-201-22/+60
* [TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek2017-09-221-1/+1
* Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"Krzysztof Parzyszek2017-09-221-1/+1
* [TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek2017-09-221-1/+1
* [TableGen] Tidy up CodeGenRegistersJaved Absar2017-09-211-28/+23
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-27/+26
* Try to fix compilation problem with libstdc++Matthias Braun2017-08-281-1/+3
* Address r311914 review commentsMatthias Braun2017-08-281-7/+5
* TableGen: Fix subreg composition/concatenationMatthias Braun2017-08-281-27/+88
* Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLaneKrzysztof Parzyszek2017-07-201-6/+2
* [TableGen][MC] Fix a few places where we didn't hide the underlying type of L...Craig Topper2017-07-141-6/+6
* Change sort function used in tblgen to be strict weak orderingDavid Green2017-06-271-1/+1
* [globalisel][tablegen] Add support for EXTRACT_SUBREG.Daniel Sanders2017-06-271-0/+78
* [TableGen] Remove code for renaming anonymous register classes as it can neve...Craig Topper2017-06-011-6/+1
* [TableGen] Print #nnn as a name of an non-native reg unit with id nnnKrzysztof Parzyszek2017-03-271-6/+13
* Implement LaneBitmask::any(), use it to replace !none(), NFCIKrzysztof Parzyszek2016-12-161-3/+3
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-29/+35
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-1/+1
* Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2016-11-301-12/+38
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-2/+1
* TableGen: Produce CoveredBySubRegs summary for register classesMatthias Braun2016-04-281-2/+5
* TableGen: Support lanemasks for classes without subregistersMatthias Braun2016-04-281-38/+50
* [TableGen] Merge the SuperClass Record and SMRange vector into a single vecto...Craig Topper2016-01-181-4/+3
* Assume lane masks are always preciseMatthias Braun2015-11-171-13/+6
* tablegen: Add a simple heuristic to get better names for pressure setsMatthias Braun2015-11-131-0/+6
* TableGen: Emit LaneMask for register classes without subregisters as ~0uMatthias Braun2015-11-101-0/+6
* [TableGen] Rename ListInit::getSize to just 'size' to be more consistent.Craig Topper2015-06-021-3/+3
* Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer2015-05-291-2/+2
* [TableGen] Remove ListInit::size() in favor of getSize() which does the same ...Craig Topper2015-05-141-2/+2
* [TableGen] Don't leak Expanders and Operators in SetTheory.Craig Topper2015-04-241-1/+1
* Change range-based for-loops to be -Wrange-loop-analysis clean.Richard Trieu2015-04-151-1/+1
* Fix AllocationPriority not getting set for derived register classes.Matthias Braun2015-03-311-1/+3
* RegAllocGreedy: Allow target to specify register class ordering.Matthias Braun2015-03-311-0/+4
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-191-0/+11
* TableGen: Fix register class lane masks being too conservative.Matthias Braun2015-03-181-1/+1
* Revert the non-cleanup part of r230769 because it introduced a non-determinis...Nick Lewycky2015-03-031-2/+0
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