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path: root/llvm/utils/TableGen/CodeGenInstruction.cpp
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* Add @earlyclobber TableGen constraintJim Grosbach2009-12-161-4/+24
| | | | llvm-svn: 91554
* whitespaceJim Grosbach2009-12-151-26/+26
| | | | llvm-svn: 91442
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-1/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng2009-10-011-0/+2
| | | | | | | | | | set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. llvm-svn: 83196
* Fix bad length argument to substr calls. Apparently I'm the first one toBob Wilson2009-08-261-2/+2
| | | | | | attempt more than 2 constraints on an instruction. llvm-svn: 80169
* Make BinOps typed and require a type specifier for !nameconcat. ThisDavid Greene2009-04-231-1/+1
| | | | | | | allows binops to be used in typed contexts such as when passing arguments to classes. llvm-svn: 69921
* Implement !nameconcat to concatenate strings and look up the resultingDavid Greene2009-04-221-1/+1
| | | | | | name in the symbol table, returning an object. llvm-svn: 69822
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-1/+1
| | | | llvm-svn: 60487
* Remove redundant word in tblgen error message.Matthijs Kooijman2008-10-271-1/+1
| | | | llvm-svn: 58250
* Handle some 64-bit atomics on x86-32, some of the time.Dale Johannesen2008-10-021-1/+2
| | | | llvm-svn: 56963
* Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman2008-05-311-2/+1
| | | | | | | | | | | index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. llvm-svn: 51808
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-291-1/+2
| | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-281-0/+1
| | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. llvm-svn: 51660
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-1/+0
| | | | llvm-svn: 48381
* Recommitting changes after more testing. These appear to cause no problems.Christopher Lamb2008-03-111-1/+1
| | | | llvm-svn: 48222
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-1/+1
| | | | llvm-svn: 48167
* Add support in TableGen for unknown operands that infer their type from the ↵Christopher Lamb2008-03-101-1/+1
| | | | | | pattern their used in. This will be used to allow insert/extract subreg patterns in .td files! llvm-svn: 48125
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-3/+3
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-081-0/+1
| | | | | | This is currently not set by anything. llvm-svn: 45748
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-071-2/+2
| | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. llvm-svn: 45687
* the name field of instructions is never set to a non-empty string, Chris Lattner2008-01-071-9/+0
| | | | | | just unconditionally use the def name of the instruction. llvm-svn: 45684
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-061-0/+280
getName() accessor. llvm-svn: 45645
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