| Commit message (Collapse) | Author | Age | Files | Lines |
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This will allow to switch to a different string storage in an upcoming
commit.
llvm-svn: 288612
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This preparation to remove SetVector.h dependency on SmallSet.h.
llvm-svn: 288256
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Patch by Daniel Cederman.
Reviewers: stoklund, arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: https://reviews.llvm.org/D27046
llvm-svn: 287856
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Summary: Depends on D25614
Reviewers: qcolombet
Subscribers: qcolombet, beanz, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D25617
llvm-svn: 287438
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No functionality change is intended.
llvm-svn: 278475
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If the result of the find is only used to compare against end(), just
use is_contained instead.
No functionality change is intended.
llvm-svn: 278469
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It's being immediately converted to a "string", but being able to tell what
type the field was originally can be useful in backends.
llvm-svn: 274575
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No functionality change intended.
llvm-svn: 272516
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will appear after a blank. This assumption does not hold in the ARM
target.
Patch by: Roger Ferrer Ibanez
Differential Revision: http://reviews.llvm.org/D20234
llvm-svn: 271666
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consider the Predicates attached to InstAlias when generating printAliasInstr.
This forces users of printAliasInstr to check those predicates beforehand.
This commit adds them in the condition set of the IAPrinter object.
Patch by: Roger Ferrer Ibanez
Differential Revision: http://reviews.llvm.org/D20233
llvm-svn: 271665
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No functionality change intended, maybe a tiny performance improvement.
llvm-svn: 270997
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llvm-svn: 261672
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mapping from instruction to unique command, instead store a list of which instructions each unique command corresponds to.
This simplifies the complexity of the code that tries to find further operands to merge into the unique command.
llvm-svn: 258656
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consumes it later. NFC
llvm-svn: 258490
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llvm-svn: 258020
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getInstructionsByEnumValue(). NFC
llvm-svn: 258018
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AsmWriterInst map. NFC
Adds the corresponding CodeGenInstruction number to each AsmWriterInst. Then write all the operand uniqueing loops using the AsmWriterInst array and indices. Then use the CodeGenInstruction index to fill out the OpCodeInfo array.
llvm-svn: 258005
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llvm-svn: 258004
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the flag in every AsmWriterOperand. NFC
llvm-svn: 257743
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the AsmMatcher uses when it overflows the 64-bit tables. No in tree targets use this code, but I tested it with an temporarily reduced table width.
llvm-svn: 257583
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64-bits for cleanliness. NFC
llvm-svn: 257582
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llvm-svn: 257581
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llvm-svn: 257580
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simple functions. NFC
llvm-svn: 257579
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allows x86 to use 56 total bits made up of a 32-bit, 16-bit, and 8-bit table. Previously we were using 64 total bits.
This saves 14K from the x86 table size. And saves space on other targets as well.
llvm-svn: 257315
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to prevent ending an array with a comma. But that's perfectly legal and not something we need to prevent. NFC
llvm-svn: 257314
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index name as an outer loop. NFC
llvm-svn: 257156
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into a vector instead of copying. NFC
llvm-svn: 257155
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AsmWriterEmitter will generate a getRegisterName function with an alternate
register name index as its second argument if the target makes use of them. The
enum of these values is generated in RegisterInfoEmitter. The getRegisterName
generator would assume the namespace could always be found by reading index 1
of the list of AltNameIndices, but this will fail if this list is sorted such
that the NoRegAltName is at index 1. Because this list is sorted by record name
(in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your
MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically
before NoRegAltName.
For example, if a target has something like
def AnAltNameIndex : RegAltNameIndex
and defines RegAltNameIndices for some registers then, prior to this change,
AsmWriterEmitter would generate references to
::AnAltNameIndex and ::NoRegAltName
Patch by Alex Bradbury!
llvm-svn: 255344
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The Statistical Profiling Extension is an optional extension to
ARMv8.2-A. Since it is an optional extension, I have added the
FeatureSPE subtarget feature to control it. The assembler-visible parts
of this extension are the new "psb csync" instruction, which is
equivalent to "hint #17", and a number of system registers.
Differential Revision: http://reviews.llvm.org/D15021
llvm-svn: 254401
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After r244870 flush() will only compare two null pointers and return,
doing nothing but wasting run time. The call is not required any more
as the stream and its SmallString are always in sync.
Thanks to David Blaikie for reviewing.
llvm-svn: 244928
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Improvement to r244212.
llvm-svn: 244252
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llvm-svn: 244212
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If the type isn't trivially moveable emplace can skip a potentially
expensive move. It also saves a couple of characters.
Call sites were found with the ASTMatcher + some semi-automated cleanup.
memberCallExpr(
argumentCountIs(1), callee(methodDecl(hasName("push_back"))),
on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))),
hasArgument(0, bindTemporaryExpr(
hasType(recordDecl(hasNonTrivialDestructor())),
has(constructExpr()))),
unless(isInTemplateInstantiation()))
No functional change intended.
llvm-svn: 238602
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per-function subtarget.
Currently, code-gen passes the default or generic subtarget to the constructors
of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which
enables some targets (AArch64, ARM, and X86) to change their instprinter's
behavior based on the subtarget feature bits. Since the backend can now use
different subtargets for each function, instprinter has to be changed to use the
per-function subtarget rather than the default subtarget.
This patch takes the first step towards enabling instprinter to change its
behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to
AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the
various print methods table-gen auto-generates.
I will follow up with changes to instprinters of AArch64, ARM, and X86.
llvm-svn: 233411
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Saves adding .str() call to any raw_ostream << SmallString usage
and a small step towards making .str() consistent in the ADTs by
removing one of the SmallString::str() use cases, discussion at
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141013/240026.html
I'll update the Phabricator patch http://reviews.llvm.org/D6372
for review of the Twine SmallString support, it's more complex
than this one.
llvm-svn: 231763
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This patch was generated by a clang tidy checker that is being open sourced.
The documentation of that checker is the following:
/// The emptiness of a container should be checked using the empty method
/// instead of the size method. It is not guaranteed that size is a
/// constant-time function, and it is generally more efficient and also shows
/// clearer intent to use empty. Furthermore some containers may implement the
/// empty method but not implement the size method. Using empty whenever
/// possible makes it easier to switch to another container in the future.
Patch by Gábor Horváth!
llvm-svn: 226161
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An instruction alias defined with InstAlias and an optional operand in the
middle of the AsmString field, "..${a} <operands>", would get the final
"}" printed in the instruction disassembly. This wouldn't happen if the optional
operand appeared as the last item in the AsmString which is how the current
backends avoided the problem.
There don't appear to be any tests for this part of Tablegen but it passes the
pre-commit tests. Manually tested the change by enabling the generic alias
printer in the ARM backend and checking the output.
Differential Revision: http://reviews.llvm.org/D6529
llvm-svn: 224348
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llvm-svn: 222958
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llvm-svn: 222782
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llvm-svn: 222781
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llvm-svn: 222780
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llvm-svn: 222779
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AsmWriter output.
llvm-svn: 222650
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to reduce total data size.
llvm-svn: 222643
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Speculative fix for a -Wframe-larger-than warning from gcc. Clang will
implicitly promote such constant arrays to globals, so in theory it
won't hit this.
llvm-svn: 213298
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inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).
Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.
The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.
llvm-svn: 210528
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llvm-svn: 210527
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When multiple aliases overlap, the correct string to print can often be
determined purely by considering the InstAlias declarations in some particular
order. This allows the user to specify that order manually when desired,
without resorting to hacking around with the default lexicographical order on
Record instantiation, which is error-prone and ugly.
I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4,
uxtw". That's only true if Rn is the stack pointer.
llvm-svn: 209199
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TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.
This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.
There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:
+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"
llvm-svn: 208969
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