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path: root/llvm/utils/TableGen/ARMDecoderEmitter.cpp
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* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-8/+3
| | | | llvm-svn: 121798
* Remove the rest of the *_sfp Neon instruction patterns.Bob Wilson2010-12-131-5/+0
| | | | | | | | | | | | | Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions. This change made a big difference in the code generated for the CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing a fine job, but some instructions that were previously moved outside the loop are not moved now. It's using fewer VFP registers now, which is generally a good thing, so I think the estimates for register pressure changed and that affected the LICM behavior. Since that isn't obviously wrong, I've just changed the test file. This completes the work for Radar 8711675. llvm-svn: 121730
* Merge DEBUG statements.Bill Wendling2010-12-131-8/+8
| | | | llvm-svn: 121660
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-3/+3
| | | | llvm-svn: 121659
* Remove reference to the CMPz instruction patterns for ARM.Jim Grosbach2010-12-071-8/+1
| | | | llvm-svn: 121180
* I did it wrong. Don't disregard these encodings here.Bill Wendling2010-12-031-7/+0
| | | | llvm-svn: 120786
* Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gprBill Wendling2010-12-031-0/+7
| | | | | | instructions. They are handled as special moves, but encoded as a normal move. llvm-svn: 120779
* The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,Jim Grosbach2010-11-301-5/+0
| | | | | | | no extra encoding information), so we no longer need to special case them here. llvm-svn: 120444
* Tidy up.Jim Grosbach2010-11-301-2/+3
| | | | llvm-svn: 120443
* Delete a few no longer needed references to pseudos.Jim Grosbach2010-11-301-4/+0
| | | | llvm-svn: 120441
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-291-6/+1
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-1/+1
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* Merge System into Support.Michael J. Spencer2010-11-291-1/+1
| | | | llvm-svn: 120298
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-5/+5
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-2/+2
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* A few 80 column cleanupsJim Grosbach2010-10-081-1/+1
| | | | llvm-svn: 116069
* Move checking for t2MOVCCi16 to the right place.Jim Grosbach2010-10-071-6/+7
| | | | llvm-svn: 115994
* Fix typo in comment.Nick Lewycky2010-10-071-1/+1
| | | | llvm-svn: 115986
* Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.Jim Grosbach2010-10-071-5/+5
| | | | llvm-svn: 115890
* Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.Jim Grosbach2010-10-071-7/+7
| | | | llvm-svn: 115884
* Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling.Jim Grosbach2010-10-061-6/+5
| | | | llvm-svn: 115841
* Fix a comment typo.Bob Wilson2010-08-271-1/+1
| | | | llvm-svn: 112302
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-111-30/+29
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-081-2/+2
| | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
* An attempt to fix the problem Anton reported withDale Johannesen2010-06-181-0/+1
| | | | | | | ARM tail calls. Don't know if it works, but it doesn't break Darwin. llvm-svn: 106309
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-1/+2
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-0/+7
| | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
* When doing Thumb disassembly, there's no need to consider ↵Johnny Chen2010-04-201-3/+6
| | | | | | | | t2ADDrSPi12/t2SUBrSPi12, as their generic counterparts t2ADDri12/t2SUBri12 should suffice. llvm-svn: 101929
* If all the bit positions are not specified; do not decode the instructions.Johnny Chen2010-04-091-9/+10
| | | | | | | | | | We are bound to fail! For proper disassembly, the well-known encoding bits of the instruction must be fully specified. This also removes pseudo instructions from considerations of disassembly, which is a better design and less fragile than the name matchings. llvm-svn: 100899
* Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargetsBob Wilson2010-04-091-0/+2
| | | | | | | | | such that the non-VFP versions have no implicit defs of VFP registers. If any callee-saved VFP registers are marked as having been defined, the prologue/epilogue code will try to save and restore them. Radar 7770432. llvm-svn: 100892
* ARM decoder emitter should print out useful information unconditionally when itJohnny Chen2010-04-091-17/+19
| | | | | | encounters decoding conflicts, instead of wrapping it inside the DEBUG() macro. llvm-svn: 100886
* Now that Evan Cheng has fixed the coalescer bug (r100804), the workaround codeJohnny Chen2010-04-081-5/+1
| | | | | | to avoid memcpy() call is no longer necessary. llvm-svn: 100811
* Various MSVC warning fixes about truncated 64 bit shifts and const pointers ↵Benjamin Kramer2010-04-081-2/+2
| | | | | | passed to free. llvm-svn: 100767
* Fix typo and correct comment somewhat.Eric Christopher2010-04-071-1/+1
| | | | llvm-svn: 100691
* Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call inJohnny Chen2010-04-071-2/+6
| | | | | | ARMDecoderEmitter.cpp, with FIXME comment. llvm-svn: 100690
* Fix a warning in GCC about a pointless typedef.Chandler Carruth2010-04-031-1/+1
| | | | llvm-svn: 100268
* Move variable "Bits" declaration/definition into the DEBUG block where its usageJohnny Chen2010-04-021-1/+2
| | | | | | is expected. llvm-svn: 100247
* Fixed build warning.Johnny Chen2010-04-021-1/+1
| | | | llvm-svn: 100244
* Change from .../Support/DataTypes.h to .../System/DataTypes.h.Johnny Chen2010-04-021-1/+1
| | | | | | (Fix build failure) llvm-svn: 100243
* Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgenJohnny Chen2010-04-021-0/+1861
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
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