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* GlobalISel: Start adding computeNumSignBits to GISelKnownBitsMatt Arsenault2020-01-061-0/+78
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* Fix Wpedantic 'extra semicolon' warning. NFC.Simon Pilgrim2019-12-211-1/+1
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* [Legalizer] Making artifact combining order-independentRoman Tereshin2019-12-131-17/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Legalization algorithm is complicated by two facts: 1) While regular instructions should be possible to legalize in an isolated, per-instruction, context-free manner, legalization artifacts can only be eliminated in pairs, which could be deeply, and ultimately arbitrary nested: { [ () ] }, where which paranthesis kind depicts an artifact kind, like extend, unmerge, etc. Such structure can only be fully eliminated by simple local combines if they are attempted in a particular order (inside out), or alternatively by repeated scans each eliminating only one innermost pair, resulting in O(n^2) complexity. 2) Some artifacts might in fact be regular instructions that could (and sometimes should) be legalized by the target-specific rules. Which means failure to eliminate all artifacts on the first iteration is not a failure, they need to be tried as instructions, which may produce more artifacts, including the ones that are in fact regular instructions, resulting in a non-constant number of iterations required to finish the process. I trust the recently introduced termination condition (no new artifacts were created during as-a-regular-instruction-retrial of artifacts not eliminated on the previous iteration) to be efficient in providing termination, but only performing the legalization in full if and only if at each step such chains of artifacts are successfully eliminated in full as well. Which is currently not guaranteed, as the artifact combines are applied only once and in an arbitrary order that has to do with the order of creation or insertion of artifacts into their worklist, which is a no particular order. In this patch I make a small change to the artifact combiner, making it to re-insert into the worklist immediate (modulo a look-through copies) artifact users of each vreg that changes its definition due to an artifact combine. Here the first scan through the artifacts worklist, while not being done in any guaranteed order, only needs to find the innermost pair(s) of artifacts that could be immediately combined out. After that the process follows def-use chains, making them shorter at each step, thus combining everything that can be combined in O(n) time. Reviewers: volkan, aditya_nandakumar, qcolombet, paquette, aemerson, dsanders Reviewed By: aditya_nandakumar, paquette Tags: #llvm Differential Revision: https://reviews.llvm.org/D71448
* [Legalizer] Refactoring out legalizeMachineFunctionRoman Tereshin2019-12-132-0/+80
| | | | | | | | and introducing new unittests/CodeGen/GlobalISel/LegalizerTest.cpp relying on it to unit test the entire legalizer algorithm (including the top-level main loop). See also https://reviews.llvm.org/D71448
* [unittests] Add InitializePasses.h includesHeejin Ahn2019-11-131-0/+1
| | | | | | | | | | | | | | Summary: After D70211, Pass.h does not include InitializePasses.h anymore, so these files need to include InitializePasses.h directly. Reviewers: rnk Subscribers: MatzeB, mehdi_amini, zzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70217
* [GISel][UnitTest] Fix a bunch of tests that were not doing anythingQuentin Colombet2019-10-112-3/+11
| | | | | | | | | | | After r368065, all the tests using GISelMITest must call setUp() before doing anything, otherwise the TargetMachine is not going to be set up. A few tests added after that commit were not doing that and ended up testing effectively nothing. Fix the setup of all the tests and fix the failing tests. llvm-svn: 374595
* [MachineIRBuilder] Fix an assertion failure with buildMergeQuentin Colombet2019-10-111-0/+39
| | | | | | | | | | | | | | | | Teach buildMerge how to deal with scalar to vector kind of requests. Prior to this patch, buildMerge would issue either a G_MERGE_VALUES when all the vregs are scalars or a G_CONCAT_VECTORS when the destination vreg is a vector. G_CONCAT_VECTORS was actually not the proper instruction when the source vregs were scalars and the compiler would assert that the sources must be vectors. Instead we want is to issue a G_BUILD_VECTOR when we are in this situation. This patch fixes that. llvm-svn: 374588
* [GISel] Allow getConstantVRegVal() to return G_FCONSTANT values.Marcello Maggioni2019-10-101-0/+168
| | | | | | | | | | | | | | | | | | | | | In GISel we have both G_CONSTANT and G_FCONSTANT, but because in GISel we don't really have a concept of Float vs Int value the only difference between the two is where the data originates from. What both G_CONSTANT and G_FCONSTANT return is just a bag of bits with the constant representation in it. By making getConstantVRegVal() return G_FCONSTANTs bit representation as well we allow ConstantFold and other things to operate with G_FCONSTANT. Adding tests that show ConstantFolding to work on mixed G_CONSTANT and G_FCONSTANT sources. Differential Revision: https://reviews.llvm.org/D68739 llvm-svn: 374458
* [GISel] Refactor and split PatternMatchTest. NFCMarcello Maggioni2019-10-093-256/+127
| | | | | | | Split the ConstantFold part into a separate file and make it use the fixture GISelMITest. llvm-svn: 374245
* [FileCheck] Remove implementation types from APIThomas Preud'homme2019-09-301-3/+2
| | | | | | | | | | | | | | | | | Summary: Remove use of FileCheckPatternContext and FileCheckString concrete types from FileCheck API to allow moving it and the other implementation only only declarations into a private header file. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68186 llvm-svn: 373211
* GlobalISel: Add G_FMAD instructionMatt Arsenault2019-09-061-0/+4
| | | | llvm-svn: 371254
* [globalisel][knownbits] Account for missing type constraintsDaniel Sanders2019-09-051-0/+26
| | | | | | | | | | | | | Now that we look through copies, it's possible to visit registers that have a register class constraint but not a type constraint. Avoid looking through copies when this occurs as the SrcReg won't be able to determine it's bit width or any known bits. Along the same lines, if the initial query is on a register that doesn't have a type constraint then the result is a default-constructed KnownBits, that is, a 1-bit fully-unknown value. llvm-svn: 371116
* [globalisel][knownbits] Correct a typo that prevented a test working as intendedDaniel Sanders2019-09-051-1/+1
| | | | llvm-svn: 371115
* [globalisel] Support trivial COPY in GISelKnownBitsDaniel Sanders2019-09-041-0/+6
| | | | | | | | | | | | | | Summary: Allow GISelKnownBits to look through the trivial case of TargetOpcode::COPY Reviewers: aditya_nandakumar Subscribers: rovka, hiraditya, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67131 llvm-svn: 370955
* GlobalISel: Add maskedValueIsZero and signBitIsZero to known bitsMatt Arsenault2019-08-291-0/+16
| | | | | | | I dropped the DemandedElts since it seems to be missing from some of the new interfaces, but not others. llvm-svn: 370389
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-153-4/+4
| | | | | | | | Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
* [GlobalISel]: Add KnownBits for G_XORAditya Nandakumar2019-08-131-0/+16
| | | | | | https://reviews.llvm.org/D66119 llvm-svn: 368648
* [GISel]: Fix a bug in KnownBits where we should have been using SizeInBitsAditya Nandakumar2019-08-121-0/+16
| | | | | | | | | https://reviews.llvm.org/D66039 We were using getIndexSize instead of getIndexSizeInBits(). Added test case for G_PTRTOINT and G_INTTOPTR. llvm-svn: 368618
* Remove leftover MF->dump()'s from r368487 that break release buildsDaniel Sanders2019-08-091-4/+0
| | | | llvm-svn: 368489
* [globalisel] Add G_SEXT_INREGDaniel Sanders2019-08-092-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Targets often have instructions that can sign-extend certain cases faster than the equivalent shift-left/arithmetic-shift-right. Such cases can be identified by matching a shift-left/shift-right pair but there are some issues with this in the context of combines. For example, suppose you can sign-extend 8-bit up to 32-bit with a target extend instruction. %1:_(s32) = G_SHL %0:_(s32), i32 24 # (I've inlined the G_CONSTANT for brevity) %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_ASHR %2:_(s32), i32 1 would reasonably combine to: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 25 which no longer matches the special case. If your shifts and extend are equal cost, this would break even as a pair of shifts but if your shift is more expensive than the extend then it's cheaper as: %2:_(s32) = G_SEXT_INREG %0:_(s32), i32 8 %3:_(s32) = G_ASHR %2:_(s32), i32 1 It's possible to match the shift-pair in ISel and emit an extend and ashr. However, this is far from the only way to break this shift pair and make it hard to match the extends. Another example is that with the right known-zeros, this: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 24 %3:_(s32) = G_MUL %2:_(s32), i32 2 can become: %1:_(s32) = G_SHL %0:_(s32), i32 24 %2:_(s32) = G_ASHR %1:_(s32), i32 23 All upstream targets have been configured to lower it to the current G_SHL,G_ASHR pair but will likely want to make it legal in some cases to handle their faster cases. To follow-up: Provide a way to legalize based on the constant. At the moment, I'm thinking that the best way to achieve this is to provide the MI in LegalityQuery but that opens the door to breaking core principles of the legalizer (legality is not context sensitive). That said, it's worth noting that looking at other instructions and acting on that information doesn't violate this principle in itself. It's only a violation if, at the end of legalization, a pass that checks legality without being able to see the context would say an instruction might not be legal. That's a fairly subtle distinction so to give a concrete example, saying %2 in: %1 = G_CONSTANT 16 %2 = G_SEXT_INREG %0, %1 is legal is in violation of that principle if the legality of %2 depends on %1 being constant and/or being 16. However, legalizing to either: %2 = G_SEXT_INREG %0, 16 or: %1 = G_CONSTANT 16 %2:_(s32) = G_SHL %0, %1 %3:_(s32) = G_ASHR %2, %1 depending on whether %1 is constant and 16 does not violate that principle since both outputs are genuinely legal. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, rovka, kristof.beyls, javed.absar, hiraditya, jrtc27, atanasyan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61289 llvm-svn: 368487
* [GISel]: Add GISelKnownBits analysisAditya Nandakumar2019-08-066-2/+78
| | | | | | | | | | | | | | https://reviews.llvm.org/D65698 This adds a KnownBits analysis pass for GISel. This was done as a pass (compared to static functions) so that we can add other features such as caching queries(within a pass and across passes) in the future. This patch only adds the basic pass boiler plate, and implements a lazy non caching knownbits implementation (ported from SelectionDAG). I've also hooked up the AArch64PreLegalizerCombiner pass to use this - there should be no compile time regression as the analysis is lazy. llvm-svn: 368065
* GlobalISel: Fix widenScalar for G_MERGE_VALUES to pointerMatt Arsenault2019-08-011-0/+38
| | | | | | | AMDGPU testcase isn't broken now, but will be in a future patch without this. llvm-svn: 367591
* GlobalISel: Add G_ATOMICRMW_{FADD|FSUB}Matt Arsenault2019-07-301-0/+30
| | | | llvm-svn: 367369
* Minor styling fix. NFC.Michael Liao2019-07-181-2/+1
| | | | llvm-svn: 366456
* GlobalISel: Handle widenScalar of arbitrary G_MERGE_VALUES sourcesMatt Arsenault2019-07-171-6/+77
| | | | | | | | | | | Extract the sources to the GCD of the original size and target size, padding with implicit_def as necessary. Also fix the case where the requested source type is wider than the original result type. This was ignoring the type, and just using the destination. Do the operation in the requested type and truncate back. llvm-svn: 366367
* GlobalISel: Handle more cases for widenScalar of G_MERGE_VALUESMatt Arsenault2019-07-171-0/+34
| | | | | | | | | | | | Use an anyext to the requested type for the leftover operand to produce a slightly wider type, and then truncate the final merge. I have another implementation almost ready which handles arbitrary widens, but I think it produces worse code in this example (which I think is 90% due to not folding redundant copies or folding out implicit_def users), so I wanted to add this as a baseline first. llvm-svn: 366366
* GlobalISel: widenScalar for G_BUILD_VECTORMatt Arsenault2019-07-081-0/+47
| | | | llvm-svn: 365320
* GlobalISel: Implement lower for min/maxMatt Arsenault2019-07-011-0/+78
| | | | llvm-svn: 364816
* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-241-8/+8
| | | | | | | | | Force using Register. One downside is the generated register enums require explicit conversion. llvm-svn: 364194
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-243-16/+16
| | | | | | | | | Avoids using a plain unsigned for registers throughoug codegen. Doesn't attempt to change every register use, just something a little more than the set needed to build after changing the return type of MachineOperand::getReg(). llvm-svn: 364191
* GlobalISel: Use the original flags when lowering fneg to fsubMatt Arsenault2019-06-171-0/+46
| | | | | | | | | | This was ignoring the flag on fneg, and using the source instruction's flags. Also fixes tests missing from r358702. Note the expansion itself isn't correct without nnan, but that should be fixed separately. llvm-svn: 363637
* [GISel]: Fix pattern matcher for m_OneUseAditya Nandakumar2019-06-141-0/+25
| | | | | | https://reviews.llvm.org/D63302 llvm-svn: 363424
* GlobalISel: Define integer min/max instructionsMatt Arsenault2019-05-171-0/+25
| | | | | | | Doesn't attempt to emit them for anything yet, but some legalizations I want to port use them. llvm-svn: 361061
* GlobalISel: Add fp<->int casts to MachineIRBuilderMatt Arsenault2019-05-171-0/+24
| | | | llvm-svn: 361019
* GlobalISel: Add MIRBuilder wrappers for bitcount instructionsMatt Arsenault2019-05-171-0/+27
| | | | | | Various expansions use these. llvm-svn: 361018
* GlobalISel: Add buildFMA to MachineIRBuilderMatt Arsenault2019-05-161-0/+3
| | | | llvm-svn: 360888
* GlobalISel: Add buildXor/buildNotMatt Arsenault2019-05-161-0/+28
| | | | llvm-svn: 360880
* GlobalISel: Add DstOp version of buildIntrinsicMatt Arsenault2019-05-161-0/+28
| | | | llvm-svn: 360879
* GlobalISel: Add buildFConstant for APFloatMatt Arsenault2019-05-161-0/+5
| | | | llvm-svn: 360853
* GlobalISel: Add some FP instructions to MachineIRBuilderMatt Arsenault2019-05-161-0/+28
| | | | | | This makes FP legalization code more convenient. llvm-svn: 360852
* [GlobalISel] Introduce a CSEConfigBase class to allow targets to define ↵Amara Emerson2019-04-151-1/+1
| | | | | | | | | | | | | | their own CSE configs. Because CodeGen can't depend on GlobalISel, we need a way to encapsulate the CSE configs that can be passed between TargetPassConfig and the targets' custom pass configs. This CSEConfigBase allows targets to create custom CSE configs which is then used by the GISel passes for the CSEMIRBuilder. This support will be used in a follow up commit to allow constant-only CSE for -O0 compiles in D60580. llvm-svn: 358368
* GlobalISel: Add another overload of buildUnmergeMatt Arsenault2019-04-051-0/+20
| | | | | | | It's annoying to have to create an array of the result type, particularly when you don't care about the size of the value. llvm-svn: 357763
* GlobalISel: Implement fewerElementsVector for phiMatt Arsenault2019-02-281-0/+94
| | | | llvm-svn: 355048
* GlobalISel: Implement moreElementsVector for bit opsMatt Arsenault2019-02-191-0/+40
| | | | llvm-svn: 354345
* GlobalISel: Fix double count of offset for irregular vector breakdownsMatt Arsenault2019-02-181-0/+48
| | | | | | | Fixes cases with odd vectors that break into multiple requested size pieces. llvm-svn: 354280
* GlobalISel: Add alignment to LegalityQuery MMOsMatt Arsenault2019-02-141-0/+49
| | | | | | | This allows targets to specify the minimum alignment required for the load/store. llvm-svn: 354071
* GlobalISel: Try to make legalize rules more useful for vectorsMatt Arsenault2019-02-071-0/+126
| | | | | | | Mostly keep the existing functions on scalars, but add versions which also operate based on the vector element size. llvm-svn: 353430
* GlobalISel: Fix not calling observer when legalizing bitcount opsMatt Arsenault2019-02-041-0/+65
| | | | | | This was hiding bugs from never legalizing the source type. llvm-svn: 353102
* GlobalISel: Fix CheckMachineFunction passing if ReadCheckFile filesMatt Arsenault2019-02-041-1/+3
| | | | | | | This could be tested, but the FileCheck library spams the error message to the console. llvm-svn: 353081
* GlobalISel: Allow constructing SrcOp/DstOp from MachineOperandMatt Arsenault2019-02-041-0/+25
| | | | llvm-svn: 353080
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