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* Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders2020-01-081-1/+1
* Revert "[MIR] Target specific MIR formating and parsing"Nico Weber2020-01-081-1/+1
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-1/+1
* Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders2020-01-081-1/+1
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-1/+1
* GlobalISel: Start adding computeNumSignBits to GISelKnownBitsMatt Arsenault2020-01-061-0/+78
* Fix Wpedantic 'extra semicolon' warning. NFC.Simon Pilgrim2019-12-211-1/+1
* [Legalizer] Making artifact combining order-independentRoman Tereshin2019-12-131-17/+159
* [Legalizer] Refactoring out legalizeMachineFunctionRoman Tereshin2019-12-132-0/+80
* [PGO][PGSO] DAG.shouldOptForSize part.Hiroshi Yamauchi2019-11-211-1/+1
* [SVE][CodeGen] Scalable vector MVT size queriesGraham Hunter2019-11-181-0/+57
* [unittests] Add InitializePasses.h includesHeejin Ahn2019-11-132-0/+2
* Fix initialization-order-fiasco error in "Add a heap alloc site marker field ...Amy Huang2019-10-311-7/+8
* Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs"Amy Huang2019-10-281-0/+140
* Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs."Amy Huang2019-10-251-144/+0
* Add an instruction marker field to the ExtraInfo in MachineInstrs.Amy Huang2019-10-251-0/+144
* Reverted r375254 as it has broken some build bots for a long time.Vladimir Vereschaka2019-10-202-235/+0
* [Codegen] Link MIRParser into CodeGenTests to fix MachineSizeOptsTest buildingRoman Lebedev2019-10-181-0/+1
* [PGO][PGSO] SizeOpts changes.Hiroshi Yamauchi2019-10-182-0/+235
* [Alignment][NFC] Use Align for TargetFrameLowering/SubtargetGuillaume Chatelet2019-10-171-1/+1
* [GISel][UnitTest] Fix a bunch of tests that were not doing anythingQuentin Colombet2019-10-112-3/+11
* [MachineIRBuilder] Fix an assertion failure with buildMergeQuentin Colombet2019-10-111-0/+39
* [GISel] Allow getConstantVRegVal() to return G_FCONSTANT values.Marcello Maggioni2019-10-101-0/+168
* [GISel] Refactor and split PatternMatchTest. NFCMarcello Maggioni2019-10-093-256/+127
* [SVE][IR] Scalable Vector size queries and IR instruction supportGraham Hunter2019-10-081-1/+1
* [FileCheck] Remove implementation types from APIThomas Preud'homme2019-09-301-3/+2
* GlobalISel: Add G_FMAD instructionMatt Arsenault2019-09-061-0/+4
* [globalisel][knownbits] Account for missing type constraintsDaniel Sanders2019-09-051-0/+26
* [globalisel][knownbits] Correct a typo that prevented a test working as intendedDaniel Sanders2019-09-051-1/+1
* [globalisel] Support trivial COPY in GISelKnownBitsDaniel Sanders2019-09-041-0/+6
* GlobalISel: Add maskedValueIsZero and signBitIsZero to known bitsMatt Arsenault2019-08-291-0/+16
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-155-8/+8
* [GlobalISel]: Add KnownBits for G_XORAditya Nandakumar2019-08-131-0/+16
* [GISel]: Fix a bug in KnownBits where we should have been using SizeInBitsAditya Nandakumar2019-08-121-0/+16
* Remove leftover MF->dump()'s from r368487 that break release buildsDaniel Sanders2019-08-091-4/+0
* [globalisel] Add G_SEXT_INREGDaniel Sanders2019-08-092-0/+143
* [GISel]: Add GISelKnownBits analysisAditya Nandakumar2019-08-066-2/+78
* [MVT][SVE] Map between scalable vector IR Type and VTsGraham Hunter2019-08-051-5/+41
* GlobalISel: Fix widenScalar for G_MERGE_VALUES to pointerMatt Arsenault2019-08-011-0/+38
* GlobalISel: Add G_ATOMICRMW_{FADD|FSUB}Matt Arsenault2019-07-301-0/+30
* Minor styling fix. NFC.Michael Liao2019-07-181-2/+1
* GlobalISel: Handle widenScalar of arbitrary G_MERGE_VALUES sourcesMatt Arsenault2019-07-171-6/+77
* GlobalISel: Handle more cases for widenScalar of G_MERGE_VALUESMatt Arsenault2019-07-171-0/+34
* [unittest] Add the missing bogus machine register info initialization.Michael Liao2019-07-091-1/+4
* [unittest] Add bogus register info.Michael Liao2019-07-091-0/+52
* GlobalISel: widenScalar for G_BUILD_VECTORMatt Arsenault2019-07-081-0/+47
* [CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used.Michael Liao2019-07-051-0/+33
* GlobalISel: Implement lower for min/maxMatt Arsenault2019-07-011-0/+78
* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-241-8/+8
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-243-16/+16
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