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* [llvm-mca] Reformat a few lines (fix spacing). NFC.Matt Davis2018-08-173-7/+5
| | | | llvm-svn: 340065
* [llvm-mca] Removed references to HWStallEvent in Scheduler.h. NFCIAndrea Di Biagio2018-08-173-23/+47
| | | | | | | | | | class Scheduler should not know anything of hardware event listeners and hardware stall events (HWStallEvent). HWStallEvent objects should only be constructed by pipeline stages to notify listeners of hardware events. No functional change intended. llvm-svn: 340036
* [llvm-mca] Fix -Wpessimizing-move warnings introduced by r339923.Andrea Di Biagio2018-08-163-4/+4
| | | | | | Reported by buildbot `clang-with-lto-ubuntu` ( build #9858 ). llvm-svn: 339928
* [llvm-mca] Refactor how execution is orchestrated by the Pipeline.Andrea Di Biagio2018-08-1614-149/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes how instruction execution is orchestrated by the Pipeline. In particular, this patch makes it more explicit how instructions transition through the various pipeline stages during execution. The main goal is to simplify both the stage API and the Pipeline execution. At the same time, this patch fixes some design issues which are currently latent, but that are likely to cause problems in future if people start defining custom pipelines. The new design assumes that each pipeline stage knows the "next-in-sequence". The Stage API has gained three new methods: - isAvailable(IR) - checkNextStage(IR) - moveToTheNextStage(IR). An instruction IR can be executed by a Stage if method `Stage::isAvailable(IR)` returns true. Instructions can move to next stages using method moveToTheNextStage(IR). An instruction cannot be moved to the next stage if method checkNextStage(IR) (called on the current stage) returns false. Stages are now responsible for moving instructions to the next stage in sequence if necessary. Instructions are allowed to transition through multiple stages during a single cycle (as long as stages are available, and as long as all the calls to `checkNextStage(IR)` returns true). Methods `Stage::preExecute()` and `Stage::postExecute()` have now become redundant, and those are removed by this patch. Method Pipeline::runCycle() is now simpler, and it correctly visits stages on every begin/end of cycle. Other changes: - DispatchStage no longer requires a reference to the Scheduler. - ExecuteStage no longer needs to directly interact with the RetireControlUnit. Instead, executed instructions are now directly moved to the next stage (i.e. the retire stage). - RetireStage gained an execute method. This allowed us to remove the dependency with the RCU in ExecuteStage. - FecthStage now updates the "program counter" during cycleBegin() (i.e. before we start executing new instructions). - We no longer need Stage::Status to be returned by method execute(). It has been dropped in favor of a more lightweight llvm::Error. Overally, I measured a ~11% performance gain w.r.t. the previous design. I also think that the Stage interface is probably easier to read now. That being said, code comments have to be improved, and I plan to do it in a follow-up patch. Differential revision: https://reviews.llvm.org/D50849 llvm-svn: 339923
* [llvm-mca] Small refactoring in preparation for another patch that will ↵Andrea Di Biagio2018-08-1612-45/+67
| | | | | | | | | | | | improve the modularity of the Pipeline. NFCI The main difference is that now `cycleStart()` and `cycleEnd()` return an llvm::Error. This patch implements a few minor style changes, and adds missing 'const' to some methods. llvm-svn: 339885
* [llvm-mca] Minor style changes. NFCAndrea Di Biagio2018-08-154-27/+28
| | | | llvm-svn: 339823
* [llvm-mca] Fix PR38575: Avoid an invalid implicit truncation of a processor ↵Andrea Di Biagio2018-08-151-1/+1
| | | | | | | | | | | | | | | | | resource mask (an uint64_t value) to unsigned. This patch fixes a regression introduced at revision 338702. A processor resource mask was incorrectly implicitly truncated to an unsigned quantity. Later on, the truncated mask was used to initialize an element of a vector of processor resource descriptors. On targets with more than 32 processor resources, some elements of the vector are left uninitialized. As a consequence, this bug might have eventually caused a crash due to null dereference in the Scheduler. This patch fixes PR38575, and adds a test for it. llvm-svn: 339768
* [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver.Matt Davis2018-08-1317-70/+131
| | | | | | | | | | | | | | | | | Summary: This patch introduces error handling to propagate the errors from llvm-mca library classes (or what will become library classes) up to the driver. This patch also introduces an enum to make clearer the intention of the return value for Stage::execute. This supports PR38101. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: llvm-commits, tschuett, gbedwell Differential Revision: https://reviews.llvm.org/D50561 llvm-svn: 339594
* [llvm-mca] Make InstrBuilder::getOrCreateInstrDesc private. NFC.Matt Davis2018-08-101-1/+2
| | | | llvm-svn: 339468
* [ADT] Normalize empty triple componentsPetr Hosek2018-08-081-1/+0
| | | | | | | | | | | | | | | | | LLVM triple normalization is handling "unknown" and empty components differently; for example given "x86_64-unknown-linux-gnu" and "x86_64-linux-gnu" which should be equivalent, triple normalization returns "x86_64-unknown-linux-gnu" and "x86_64--linux-gnu". autoconf's config.sub returns "x86_64-unknown-linux-gnu" for both "x86_64-linux-gnu" and "x86_64-unknown-linux-gnu". This changes the triple normalization to behave the same way, replacing empty triple components with "unknown". This addresses PR37129. Differential Revision: https://reviews.llvm.org/D50219 llvm-svn: 339294
* [llvm-mca] Speed up the computation of the wait/ready/issued sets in the ↵Andrea Di Biagio2018-08-034-100/+114
| | | | | | | | | | | | | | Scheduler. This patch is a follow-up to r338702. We don't need to use a map to model the wait/ready/issued sets. It is much more efficient to use a vector instead. This patch gives us an average 7.5% speedup (on top of the ~12% speedup obtained after r338702). llvm-svn: 338883
* [llvm-mca] Use a vector to store ResourceState objects in the ResourceManager.Andrea Di Biagio2018-08-022-81/+70
| | | | | | | | | | | | | | | We don't need to use a map to store ResourceState objects. The number of processor resources is known statically from the scheduling model. We can therefore use a vector, and reserve a slot for each processor resource that we want to simulate. Every time the ResourceManager queries the ResourceState vector, the index to the vector of ResourceState objects can be easily computed from the processor resource mask. This drastically reduces the time complexity of method ResourceManager::use() and method ResourceManager::release(). This patch gives an average speedup of 12%. llvm-svn: 338702
* [llvm-mca] Correctly update the rank in `Scheduler::select()`.Andrea Di Biagio2018-08-011-1/+3
| | | | | | Found by inspection. llvm-svn: 338579
* [llvm-mca] Improve code comments. NFC.Andrea Di Biagio2018-08-012-2/+2
| | | | llvm-svn: 338513
* [llvm-mca] Update the help text to reflect "physical" registers. NFC.Matt Davis2018-07-311-1/+1
| | | | llvm-svn: 338430
* [llvm-mca] Remove README.txtAndrea Di Biagio2018-07-311-865/+0
| | | | | | | | | | | | | | | | A detailed description of the tool has been recently added by Matt to CommandGuide/llvm-mca.rst. File README.txt is now redundant and can be removed; all the relevant user-guide information has been improved and then moved to llvm-mca.rst. In future, we should add another .rst for the "llvm-mca developer manual" to provide infromation about: - llvm-mca internals. - How to add custom stages to the simulated pipeline. - How to provide extra processor info in the scheduling model to improve the analysis performed by llvm-mca. llvm-svn: 338386
* [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms.Andrea Di Biagio2018-07-314-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches llvm-mca how to identify dependency breaking instructions on btver2. An example of dependency breaking instructions is the zero-idiom XOR (example: `XOR %eax, %eax`), which always generates zero regardless of the actual value of the input register operands. Dependency breaking instructions don't have to wait on their input register operands before executing. This is because the computation is not dependent on the inputs. Not all dependency breaking idioms are also zero-latency instructions. For example, `CMPEQ %xmm1, %xmm1` is independent on the value of XMM1, and it generates a vector of all-ones. That instruction is not eliminated at register renaming stage, and its opcode is issued to a pipeline for execution. So, the latency is not zero. This patch adds a new method named isDependencyBreaking() to the MCInstrAnalysis interface. That method takes as input an instruction (i.e. MCInst) and a MCSubtargetInfo. The default implementation of isDependencyBreaking() conservatively returns false for all instructions. Targets may override the default behavior for specific CPUs, and return a value which better matches the subtarget behavior. In future, we should teach to Tablegen how to automatically generate the body of isDependencyBreaking from scheduling predicate definitions. This would allow us to expose the knowledge about dependency breaking instructions to the machine schedulers (and, potentially, other codegen passes). Differential Revision: https://reviews.llvm.org/D49310 llvm-svn: 338372
* [MCA] Avoid an InstrDesc copy in mca::LSUnit::reserve.Dean Michael Berris2018-07-261-1/+1
| | | | | | | | | | | | | | | | | | Summary: InstrDesc contains 4 vectors (as well as some other data), so it's expensive to copy. Authored By: orodley Reviewers: andreadb, mattd, dberris Reviewed By: mattd, dberris Subscribers: dberris, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D49775 llvm-svn: 337985
* [llvm-mca][BtVer2] teach how to identify false dependencies on partially writtenAndrea Di Biagio2018-07-154-58/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers. The goal of this patch is to improve the throughput analysis in llvm-mca for the case where instructions perform partial register writes. On x86, partial register writes are quite difficult to model, mainly because different processors tend to implement different register merging schemes in hardware. When the code contains partial register writes, the IPC (instructions per cycles) estimated by llvm-mca tends to diverge quite significantly from the observed IPC (using perf). Modern AMD processors (at least, from Bulldozer onwards) don't rename partial registers. Quoting Agner Fog's microarchitecture.pdf: " The processor always keeps the different parts of an integer register together. For example, AL and AH are not treated as independent by the out-of-order execution mechanism. An instruction that writes to part of a register will therefore have a false dependence on any previous write to the same register or any part of it." This patch is a first important step towards improving the analysis of partial register updates. It changes the semantic of RegisterFile descriptors in tablegen, and teaches llvm-mca how to identify false dependences in the presence of partial register writes (for more details: see the new code comments in include/Target/TargetSchedule.h - class RegisterFile). This patch doesn't address the case where a write to a part of a register is followed by a read from the whole register. On Intel chips, high8 registers (AH/BH/CH/DH)) can be stored in separate physical registers. However, a later (dirty) read of the full register (example: AX/EAX) triggers a merge uOp, which adds extra latency (and potentially affects the pipe usage). This is a very interesting article on the subject with a very informative answer from Peter Cordes: https://stackoverflow.com/questions/45660139/how-exactly-do-partial-registers-on-haswell-skylake-perform-writing-al-seems-to In future, the definition of RegisterFile can be extended with extra information that may be used to identify delays caused by merge opcodes triggered by a dirty read of a partial write. Differential Revision: https://reviews.llvm.org/D49196 llvm-svn: 337123
* [llvm-mca] Turn InstructionTables into a Stage.Matt Davis2018-07-144-77/+61
| | | | | | | | | | | | | | | | | Summary: This patch converts the InstructionTables class into a subclass of mca::Stage. This change allows us to use the Stage's inherited Listeners for event notifications. This also allows us to create a simple pipeline for viewing the InstructionTables report. I have been working on a follow on patch that should cleanup addView in InstructionTables. Right now, addView adds the view to both the Listener list and Views list. The follow-on patch addresses the fact that we don't really need two lists in this case. That change is not specific to just InstructionTables, so it will be a separate patch. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D49329 llvm-svn: 337113
* [llvm-mca] Remove unused InstRef formal from pre and post execute callbacks. ↵Matt Davis2018-07-145-12/+12
| | | | | | NFC. llvm-svn: 337077
* [llvm-mca] Improve a few debug prints. NFCAndrea Di Biagio2018-07-136-22/+24
| | | | llvm-svn: 337003
* [llvm-mca] Simplify the Pipeline constructor. NFCAndrea Di Biagio2018-07-132-7/+2
| | | | llvm-svn: 336984
* [llvm-mca] Removed unused arguments from methods in class Pipeline. NFCAndrea Di Biagio2018-07-132-14/+15
| | | | llvm-svn: 336983
* [llvm-mca] Constify SourceMgr::hasNext. NFC.Matt Davis2018-07-121-1/+1
| | | | llvm-svn: 336961
* [llvm-mca] Add cycleBegin/cycleEnd callbacks to mca::Stage.Matt Davis2018-07-1211-13/+40
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch clears up some of the semantics within the Stage class. Now, preExecute can be called multiple times per simulated cycle. Previously preExecute was only called once per cycle, and postExecute could have been called multiple times. Now, cycleStart/cycleEnd are called only once per simulated cycle. preExecute/postExecute can be called multiple times per cycle. This occurs because multiple execution events can occur during a single cycle. When stages are executed (Pipeline::runCycle), the postExecute hook will be called only if all Stages return a success from their 'execute' callback. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D49250 llvm-svn: 336959
* [llvm-mca] Simplify eventing by adding an onEvent templated method.Matt Davis2018-07-1222-46/+40
| | | | | | | | | | | | | | | | | | | | Summary: This patch eliminates some redundancy in iterating across Listeners for the Instruction and Stall HWEvents, by introducing a template onEvent routine. This change was suggested by @courbet in https://reviews.llvm.org/D48576. I hope that this patch addresses that suggestion appropriately. I do like this change better than what we had previously. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb, courbet Subscribers: javed.absar, tschuett, gbedwell, llvm-commits, courbet Differential Revision: https://reviews.llvm.org/D48672 llvm-svn: 336916
* [llvm-mca] Use a different character to flag instructions with side-effects ↵Andrea Di Biagio2018-07-111-2/+2
| | | | | | | | | | | | | | | | | | | | | in the Instruction Info View. NFC This makes easier to identify changes in the instruction info flags. It also helps spotting potential regressions similar to the one recently introduced at r336728. Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and spaces. A change in position of the flag marker may not trigger a test failure. This patch only changes the character used for flag `hasSideEffects`. The reason why I didn't touch other flags is because I want to avoid spamming the mailing because of the massive diff due to the numerous tests affected by this change. In future, each instruction flag should be associated with a different character in the Instruction Info View. llvm-svn: 336797
* [llvm-mca] report an error if the assembly sequence contains an unsupported ↵Andrea Di Biagio2018-07-093-25/+46
| | | | | | | | | | | | | instruction. This is a short-term fix for PR38093. For now, we llvm::report_fatal_error if the instruction builder finds an unsupported instruction in the instruction stream. We need to revisit this fix once we start addressing PR38101. Essentially, we need a better framework for error handling. llvm-svn: 336543
* [llvm-mca] Add HardwareUnit and Context classes.Matt Davis2018-07-069-25/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the construction of the default backend from llvm-mca.cpp and into mca::Context. The Context class is responsible for holding ownership of the simulated hardware components. These components are subclasses of HardwareUnit. Right now the HardwareUnit is pretty bare-bones, but eventually we might want to add some common functionality across all hardware components, such as isReady() or something similar. I have a feeling this patch will probably need some updates, but it's a start. One thing I am not particularly fond of is the rather large interface for createDefaultPipeline. That convenience routine takes a rather large set of inputs from the llvm-mca driver, where many of those inputs are generated via command line options. One item I think we might want to change is the separating of ownership of hardware components (owned by the context) and the pipeline (which owns Stages). In short, a Pipeline owns Stages, a Context (currently) owns hardware. The Pipeline's Stages make use of the components, and thus there is a lifetime dependency generated. The components must outlive the pipeline. We could solve this by having the Context also own the Pipeline, and not return a unique_ptr<Pipeline>. Now that I think about it, I like that idea more. Differential Revision: https://reviews.llvm.org/D48691 llvm-svn: 336456
* [llvm-mca] A write latency cannot be a negative value. NFCAndrea Di Biagio2018-07-063-10/+10
| | | | llvm-svn: 336437
* [llvm-mca] improve the instruction issue logic implemented by the Scheduler.Andrea Di Biagio2018-07-062-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the Scheduler heuristic used to select the next instruction to issue to the pipelines. The motivating example is test X86/BtVer2/add-sequence.s, for which llvm-mca wrongly reported an estimated IPC of 1.50. According to perf, the actual IPC for that test should have been ~2.00. It turns out that an IPC of 2.00 for test add-sequence.s cannot possibly be predicted by a Scheduler that only prioritizes instructions based on their "age". A similar issue also affected test X86/BtVer2/dependent-pmuld-paddd.s, for which llvm-mca wrongly estimated an IPC of 0.84 instead of an IPC of 1.00. Instructions in the ReadyQueue are now ranked based on two factors: - The "age" of an instruction. - The number of unique users of writes associated with an instruction. The new logic still prioritizes older instructions over younger instructions to minimize the pressure on the reorder buffer. However, the number of users of an instruction now also affects the overall rank. This potentially increases the ability of the Scheduler to extract instruction level parallelism. This patch fixes the problem with the wrong IPC reported for test add-sequence.s and test dependent-pmuld-paddd.s. llvm-svn: 336420
* [llvm-mca] Fix RegisterFile debug prints. NFCAndrea Di Biagio2018-07-052-3/+9
| | | | llvm-svn: 336367
* [llvm-mca] Clear the content of map VariantDescriptors in InstrBuilder ↵Andrea Di Biagio2018-07-022-0/+5
| | | | | | | | | | | | | | before we start analyzing a new CodeBlock. NFCI. Different CodeBlocks don't overlap. The same MCInst cannot appear in more than one code block because all blocks are instantiated before the simulation is run. We should always clear the content of map VariantDescriptors before every simulation, since VariantDescriptors cannot possibly store useful information for the next blocks. It is also "safer" to clear its content because `MCInst*` is used as the key type for map VariantDescriptors. llvm-svn: 336142
* [MC] Error on a .zerofill directive in a non-virtual sectionFrancis Visoiu Mistrih2018-07-021-1/+2
| | | | | | | | | | | | | | | On darwin, all virtual sections have zerofill type, and having a .zerofill directive in a non-virtual section is not allowed. Instead of asserting, show a nicer error. In order to use the equivalent of .zerofill in a non-virtual section, the usage of .zero of .space is required. This patch replaces the assert with an error. Differential Revision: https://reviews.llvm.org/D48517 llvm-svn: 336127
* [llvm-mca] Remove field HasReadAdvanceEntries from class ReadDescriptor.Andrea Di Biagio2018-06-293-15/+0
| | | | | | | | | | | | This simplifies the logic that updates RAW dependencies in the DispatchStage. There is no advantage in storing that flag in the ReadDescriptor; we should simply rely on the call to `STI.getReadAdvanceCycles()` to obtain the ReadAdvance cycles. If there are no read-advance entries, then method `getReadAdvanceCycles()` quickly returns 0. No functional change intended. llvm-svn: 335977
* [llvm-mca] Delete Pipeline's copy ctor and assignement operator.Matt Davis2018-06-281-0/+3
| | | | | | Prevent copying of the Pipeline. llvm-svn: 335885
* [llvm-mca] Use a WriteRef to describe register writes in class RegisterFile.Andrea Di Biagio2018-06-286-50/+103
| | | | | | | | | | | This patch introduces a new class named WriteRef. A WriteRef is used by the RegisterFile to keep track of register definitions. Internally it wraps a WriteState, as well as the source index of the defining instruction. This patch allows the tool to propagate additional information to support future analysis on data dependencies. llvm-svn: 335867
* [llvm-mca] Refactor method RegisterFile::collectWrites(). NFCIAndrea Di Biagio2018-06-281-7/+13
| | | | | | | | | | | | Rather than calling std::find in a loop, just sort the vector and remove duplicate entries at the end of the function. Also, move the debug print at the end of the function, and query the MCRegisterInfo to print register names rather than physreg IDs. No functional change intended. llvm-svn: 335837
* [llvm-mca] Register listeners with stages; remove Pipeline dependency from ↵Matt Davis2018-06-2711-71/+49
| | | | | | | | | | | | | | | | | | | | | | | | Stage. Summary: This patch removes a few callbacks from Pipeline. It comes at the cost of registering Listeners with all Stages. Not all stages need listeners or issue callbacks, this registration is a bit redundant. However, as we build-out the API, this redundancy can disappear. The main purpose here is to move callback code from the Pipeline and into the stages that actually issue those callbacks. This removes the back-pointer to the Pipeline that was put into a few Stage subclasses. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb, courbet Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48576 llvm-svn: 335748
* [llvm-mca] Avoid calling method update() on instructions that are already in ↵Andrea Di Biagio2018-06-273-15/+25
| | | | | | | | | | the IS_READY state. NFCI When promoting instructions from the wait queue to the ready queue, we should check if an instruction has already reached the IS_READY state before calling method update(). llvm-svn: 335722
* [llvm-mca] Add a comment to Stage::execute and fix a spelling error. NFC.Matt Davis2018-06-271-1/+3
| | | | llvm-svn: 335697
* [llvm-mca] Removed wrong NDEBUG guards introduced by my last commit.Andrea Di Biagio2018-06-264-10/+0
| | | | | | This partially reverts r335589. llvm-svn: 335592
* [llvm-mca] Remove unused header files and correctly guard some include ↵Andrea Di Biagio2018-06-267-8/+19
| | | | | | headers under NDEBUG. NFC llvm-svn: 335589
* [llvm-mca] Rename Backend to Pipeline. NFC.Matt Davis2018-06-2522-96/+97
| | | | | | | | | | | | | | | | | | Summary: This change renames the Backend and BackendPrinter to Pipeline and PipelinePrinter respectively. Variables and comments have also been updated to reflect this change. The reason for this rename, is to be slightly more correct about what MCA is modeling. MCA models a Pipeline, which implies some logical sequence of stages. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb, courbet Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48496 llvm-svn: 335496
* [llvm-mca] Remove unnecessary include and forward decl in RCU. NFC.Matt Davis2018-06-222-5/+3
| | | | | | | The DispatchUnit is no longer a dependency of RCU, so this patch removes a stale include and forward decl. This patch also cleans up some comments. llvm-svn: 335392
* [llvm-mca] Remove redundant call. NFCAndrea Di Biagio2018-06-221-2/+0
| | | | llvm-svn: 335368
* [llvm-mca] Set the operand ID for implicit register reads/writes. NFCAndrea Di Biagio2018-06-222-36/+43
| | | | | | | Also, move the definition of InstRef at the end of Instruction.h to avoid a forward declaration. llvm-svn: 335363
* [llvm-mca] Introduce a sequential container of StagesMatt Davis2018-06-2210-74/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Remove explicit stages and introduce a list of stages. A pipeline should be composed of an arbitrary list of stages, and not any predefined list of stages in the Backend. The Backend should not know of any particular stage, rather it should only be concerned that it has a list of stages, and that those stages will fulfill the contract of what it means to be a Stage (namely pre/post/execute a given instruction). For now, we leave the original set of stages defined in the Backend ctor; however, I imagine these will be moved out at a later time. This patch makes an adjustment to the semantics of Stage::isReady. Specifically, what the Backend really needs to know is if a Stage has unfinished work. With that said, it is more appropriately renamed Stage::hasWorkToComplete(). This change will clean up the check in Backend::run(), allowing us to query each stage to see if there is unfinished work, regardless of what subclass a stage might be. I feel that this change simplifies the semantics too, but that's a subjective statement. Given how RetireStage and ExecuteStage handle data in their preExecute(), I've had to change the order of Retire and Execute in our stage list. Retire must complete any of its preExecute actions before ExecuteStage's preExecute can take control. This is mainly because both stages utilize the RCU. In the meantime, I want to see if I can adjust that or remove that coupling. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46907 llvm-svn: 335361
* [llvm-mca] Updates comment in code, and remove some stale comments. NFCAndrea Di Biagio2018-06-214-145/+81
| | | | | | | Also, rename fields `TotalMappings` and `NumUsedMappings` in struct RegisterMappingTracker into `NumPhysRegs` and `NumUsedPhysRegs`. llvm-svn: 335219
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