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* [llvm-mca] Account for buffered resources when analyzing "Super" resources.Andrea Di Biagio2018-11-091-1/+28
| | | | | | | | | | | | | | | | | | | | This was noticed when working on PR3946. By construction, a group cannot be used as a "Super" resource. That constraint is enforced by method `SubtargetEmitter::ExpandProcResource()`. A Super resource S can be part of a group G. However, method `SubtargetEmitter::ExpandProcResource()` would not update the number of consumed resource cycles in G based on S. In practice, this is perfectly fine because the resource usage is correctly computed for processor resource units. However, llvm-mca should still check if G is a buffered resource. Before this patch, llvm-mca didn't correctly check if S was part of a group that defines a buffer. So, the instruction descriptor was not correctly set. For now, the semantic change introduced by this patch doesn't affect any of the upstream scheduling models. However, it will allow to make some progress on PR3946. llvm-svn: 346545
* [llvm-mca] Use a small vector for instructions in the EntryStage.Andrea Di Biagio2018-11-093-11/+15
| | | | | | | | | | | | | | | | | | | | | Use a simple SmallVector to track the lifetime of simulated instructions. An ordered map was not needed because instructions are already picked in program order. It is also much faster if we avoid searching for already retired instructions at the end of every cycle. The new policy only triggers a "garbage collection" when the number of retired instructions becomes significantly big when compared with the total size of the vector. While working on this, I noticed that instructions were correctly retired, but their internal state was not updated (i.e. there was no transition from the EXECUTED state, to the RETIRED state). While this was not a problem for the views, it prevented the EntryStage from correctly garbage collecting already retired instructions. That was a bad oversight, and this patch fixes it. The observed speedup on a debug build of llvm-mca after this patch is ~6%. On a release build of llvm-mca, the observed speedup is ~%15%. llvm-svn: 346487
* [llvm-mca] Partially revert r346417.Matt Davis2018-11-081-16/+19
| | | | | | | Restored the llvm:: namespace qualifier on make_unique. This removes the ambiguity with make_unique. llvm-svn: 346424
* [llvm-mca] PR39261: Rename FetchStage to EntryStage.Andrea Di Biagio2018-11-085-22/+23
| | | | | | | | | | | | This fixes PR39261. FetchStage is a misnomer. It causes confusion with the frontend fetch stage, which we don't currently simulate. I decided to rename it into EntryStage mainly because this is meant to be a "source" stage for all pipelines. Differential Revision: https://reviews.llvm.org/D54268 llvm-svn: 346419
* [llvm-mca] Remove unneeded namespace qualifier. NFC.Matt Davis2018-11-081-24/+21
| | | | llvm-svn: 346417
* [llvm-mca] Move the AssembleInput logic into its own class.Matt Davis2018-11-075-103/+218
| | | | | | | | | | | | | | | | | Summary: This patch introduces a CodeRegionGenerator class which is responsible for parsing some type of input and creating a 'CodeRegions' instance for use by llvm-mca. In the future, we will also have a CodeRegionGenerator subclass for converting an input object file into CodeRegions. For now, we only have the subclass for converting input assembly into CodeRegions. This is mostly a NFC patch, as the logic remains close to the original, but now encapsulated in its own class and moved outside of llvm-mca.cpp. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: mgorny, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D54179 llvm-svn: 346344
* [llvm-mca] Add extra counters for move elimination in view ↵Andrea Di Biagio2018-11-017-47/+163
| | | | | | | | | | | | | | | | | | RegisterFileStatistics. This patch teaches view RegisterFileStatistics how to report events for optimizable register moves. For each processor register file, view RegisterFileStatistics reports the following extra information: - Number of optimizable register moves - Number of register moves eliminated - Number of zero moves (i.e. register moves that propagate a zero) - Max Number of moves eliminated per cycle. Differential Revision: https://reviews.llvm.org/D53976 llvm-svn: 345865
* [llvm-mca] Remove the verb 'assemble' from a few options in help. NFC.Matt Davis2018-10-311-17/+17
| | | | | | | * MCA does not assemble anything. * Ran clang-format. llvm-svn: 345750
* [llvm-mca] Remove namespace prefixes made redundant by r345612. NFCAndrea Di Biagio2018-10-3118-149/+129
| | | | llvm-svn: 345730
* [llvm-mca] Move namespace mca inside llvm::Fangrui Song2018-10-3059-42/+118
| | | | | | | | | | | | | | | | Summary: This allows to remove `using namespace llvm;` in those *.cpp files When we want to revisit the decision (everything resides in llvm::mca::*) in the future, we can move things to a nested namespace of llvm::mca::, to conceptually make them separate from the rest of llvm::mca::* Reviewers: andreadb, mattd Reviewed By: andreadb Subscribers: javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D53407 llvm-svn: 345612
* [llvm-mca] Lower to mca::Instructon before the pipeline is run.Andrea Di Biagio2018-10-297-59/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change, the lowering of instructions from llvm::MCInst to mca::Instruction was done as part of the first stage of the pipeline (i.e. the FetchStage). In particular, FetchStage was responsible for picking the next instruction from the source sequence, and lower it to an mca::Instruction with the help of an object of class InstrBuilder. The dependency on InstrBuilder was problematic for a number of reasons. Class InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction. That means, it is hard to support a different scenario where instructions in input are not instances of class llvm::MCInst. Even if we managed to specialize InstrBuilder, and generalize most of its internal logic, the dependency on InstrBuilder in FetchStage would have caused more troubles (other than complicating the pipeline logic). With this patch, the lowering step is done before the pipeline is run. The pipeline is no longer responsible for lowering from MCInst to mca::Instruction. As a consequence of this, the FetchStage no longer needs to interact with an InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a sequence of mca::Instruction objects. This simplifies the logic of FetchStage, and increases the usability of it. As a result, on a debug build, we see a 7-9% speedup; on a release build, the speedup is around 3-4%. llvm-svn: 345500
* [llvm-mca] Fix -wreorder and -Wunused-private-field after r345376. NFCSam McCall2018-10-262-4/+2
| | | | llvm-svn: 345378
* [llvm-mca] Removed dependency on mca::SourcMgr in some Views. NFCAndrea Di Biagio2018-10-269-44/+61
| | | | llvm-svn: 345376
* [llvm-mca] Introduce a new base class for mca::Instruction, and change how ↵Andrea Di Biagio2018-10-255-79/+84
| | | | | | | | | | | | | | | | | | | | | read/write information is stored. This patch introduces a new base class for Instruction named InstructionBase. Class InstructionBase is responsible for tracking data dependencies with the help of ReadState and WriteState objects. Class Instruction now derives from InstructionBase, and adds extra information related to the `InstrStage` as well as the `RCUTokenID`. ReadState and WriteState objects are no longer unique pointers. This avoids extra heap allocation and pointer checks that weren't really needed. Now, those objects are simply stored into SmallVectors. We use a SmallVector instead of a std::vector because we expect most instructions to only have a very small number of reads and writes. By using a simple SmallVector we also avoid extra heap allocations most of the time. In a debug build, this improves the performance of llvm-mca by roughly 10% (I still have to verify the impact in performance on a release build). llvm-svn: 345280
* [llvm-mca] Removed a couple of redundant method declarations, and simplified ↵Andrea Di Biagio2018-10-257-38/+23
| | | | | | code in ResourcePressureView. NFC llvm-svn: 345259
* [llvm-mca] Replace InstRef::isValid with operator bool. NFC.Matt Davis2018-10-246-17/+12
| | | | llvm-svn: 345190
* [llvm-mca] Simplify the logic in FetchStage. NFCIAndrea Di Biagio2018-10-243-22/+18
| | | | | | Only method 'getNextInstruction()' needs to interact with the SourceMgr. llvm-svn: 345185
* [llvm-mca] Remove dependency from InstrBuilder in class InstructionTables.Andrea Di Biagio2018-10-246-12/+9
| | | | | | | | | Also, removed the initialization of vectors used for processor resource masks. Support function 'computeProcResourceMasks()' already calls method resize on those vectors. No functional change intended. llvm-svn: 345161
* [llvm-mca] Refactor class SourceMgr. NFCIAndrea Di Biagio2018-10-244-44/+43
| | | | | | | | Added begin()/end() methods to allow the usage of SourceMgr in foreach loops. With this change, method getMCInstFromIndex() (as well as a couple of other methods) are now redundant, and can be removed from the public interface. llvm-svn: 345147
* [llvm-mca] [llvm-mca] Improved error handling and error reporting from class ↵Andrea Di Biagio2018-10-244-47/+78
| | | | | | | | | | | | | | | | | | | | | | | | | InstrBuilder. A new class named InstructionError has been added to Support.h in order to improve the error reporting from class InstrBuilder. The llvm-mca driver is responsible for handling InstructionError objects, and printing them out to stderr. The goal of this patch is to remove all the remaining error handling logic from the library code. In particular, this allows us to: - Simplify the logic in InstrBuilder by removing a needless dependency from MCInstrPrinter. - Centralize all the error halding logic in a new function named 'runPipeline' (see llvm-mca.cpp). This is also a first step towards generalizing class InstrBuilder, so that in future, we will be able to reuse its logic to also "lower" MachineInstr to mca::Instruction objects. Differential Revision: https://reviews.llvm.org/D53585 llvm-svn: 345129
* [llvm-mca] Remove a couple of using directives and a bunch of redundant ↵Andrea Di Biagio2018-10-227-16/+13
| | | | | | namespace llvm prefixes. NFC llvm-svn: 344916
* [llvm-mca] Use llvm::ArrayRef in class SourceMgr. NFCIAndrea Di Biagio2018-10-225-33/+31
| | | | | | | Class SourceMgr now uses type ArrayRef<MCInst> to reference the sequence of code from a "CodeRegion". llvm-svn: 344911
* [llvm-mca] Remove a stale TODO comment. NFCAndrea Di Biagio2018-10-191-2/+0
| | | | | | | Starting from revision r344334, we can now describe optimizable register-register moves in the machine scheduling models. llvm-svn: 344797
* Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFCFangrui Song2018-10-191-7/+6
| | | | llvm-svn: 344774
* [llvm-mca] Correctly set aliases for register writes introduced by optimized ↵Andrea Di Biagio2018-10-123-16/+72
| | | | | | | | | | | register moves. This fixes a problem introduced by r344334. A write from a non-zero move eliminated at register renaming stage was not correctly handled by the PRF. This would have led to an assertion failure if the processor model declares a PRF that enables non-zero move elimination. llvm-svn: 344392
* [llvm-mca] Remove method ↵Andrea Di Biagio2018-10-122-7/+3
| | | | | | RegisterFileStatistics::initializeRegisterFileInfo(). NFC llvm-svn: 344339
* [tblgen][llvm-mca] Add the ability to describe move elimination candidates ↵Andrea Di Biagio2018-10-122-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | via tablegen. This patch adds the ability to identify instructions that are "move elimination candidates". It also allows scheduling models to describe processor register files that allow move elimination. A move elimination candidate is an instruction that can be eliminated at register renaming stage. Each subtarget can specify which instructions are move elimination candidates with the help of tablegen class "IsOptimizableRegisterMove" (see llvm/Target/TargetInstrPredicate.td). For example, on X86, BtVer2 allows both GPR and MMX/SSE moves to be eliminated. The definition of 'IsOptimizableRegisterMove' for BtVer2 looks like this: ``` def : IsOptimizableRegisterMove<[ InstructionEquivalenceClass<[ // GPR variants. MOV32rr, MOV64rr, // MMX variants. MMX_MOVQ64rr, // SSE variants. MOVAPSrr, MOVUPSrr, MOVAPDrr, MOVUPDrr, MOVDQArr, MOVDQUrr, // AVX variants. VMOVAPSrr, VMOVUPSrr, VMOVAPDrr, VMOVUPDrr, VMOVDQArr, VMOVDQUrr ], CheckNot<CheckSameRegOperand<0, 1>> > ]>; ``` Definitions of IsOptimizableRegisterMove from processor models of a same Target are processed by the SubtargetEmitter to auto-generate a target-specific override for each of the following predicate methods: ``` bool TargetSubtargetInfo::isOptimizableRegisterMove(const MachineInstr *MI) const; bool MCInstrAnalysis::isOptimizableRegisterMove(const MCInst &MI, unsigned CPUID) const; ``` By default, those methods return false (i.e. conservatively assume that there are no move elimination candidates). Tablegen class RegisterFile has been extended with the following information: - The set of register classes that allow move elimination. - Maxium number of moves that can be eliminated every cycle. - Whether move elimination is restricted to moves from registers that are known to be zero. This patch is structured in three part: A first part (which is mostly boilerplate) adds the new 'isOptimizableRegisterMove' target hooks, and extends existing register file descriptors in MC by introducing new fields to describe properties related to move elimination. A second part, uses the new tablegen constructs to describe move elimination in the BtVer2 scheduling model. A third part, teaches llm-mca how to query the new 'isOptimizableRegisterMove' hook to mark instructions that are candidates for move elimination. It also teaches class RegisterFile how to describe constraints on move elimination at PRF granularity. llvm-mca tests for btver2 show differences before/after this patch. Differential Revision: https://reviews.llvm.org/D53134 llvm-svn: 344334
* [tblgen][CodeGenSchedule] Add a check for invalid RegisterFile definitions ↵Andrea Di Biagio2018-10-111-6/+4
| | | | | | with zero physical registers. llvm-svn: 344235
* [llvm-mca] Minor refactoring in preparation for a patch that will fully fix ↵Andrea Di Biagio2018-10-102-12/+15
| | | | | | PR36671. NFCI llvm-svn: 344149
* [llvm-mca] Remove unused/stale forward decl. NFC.Matt Davis2018-10-041-2/+0
| | | | llvm-svn: 343823
* [llvm-mca] Move field 'AllowZeroMoveEliminationOnly' to class RegisterFile. NFC.Andrea Di Biagio2018-10-042-5/+23
| | | | | | | | | | | | | | | | Flag 'AllowZeroMoveEliminationOnly' should have been a property of the PRF, and not set at register granularity. This change also restricts move elimination to writes that update a full physical register. We assume that there is a strong correlation between logical registers that allow move elimination, and how those same registers are allocated to physical registers by the register renamer. This is still a no functional change, because this experimental code path is disabled for now. This is done in preparation for another patch that will add the ability to describe how move elimination works in scheduling models. llvm-svn: 343787
* [llvm-mca] Check for inconsistencies when constructing instruction descriptors.Andrea Di Biagio2018-10-044-2/+43
| | | | | | | This should help with catching inconsistent definitions of instructions with zero opcodes, which also declare to consume scheduler/pipeline resources. llvm-svn: 343766
* [llvm-mca] Add support for move elimination in class RegisterFile.Andrea Di Biagio2018-10-037-10/+164
| | | | | | | | | | | | | | | | | | | This patch teaches class RegisterFile how to analyze register writes from instructions that are move elimination candidates. In particular, it teaches it how to check if a move can be effectively eliminated by the underlying PRF, and (if necessary) how to perform move elimination. The long term goal is to allow processor models to describe instructions that are valid move elimination candidates. The idea is to let register file definitions in tablegen declare if/when moves can be eliminated. This patch is a non functional change. The logic that performs move elimination is currently disabled. A future patch will add support for move elimination in the processor models, and enable this new code path. llvm-svn: 343691
* [llvm-mca] Remove unecessary forward decls. NFC.Matt Davis2018-10-024-5/+0
| | | | | | This patch also removes an unecessary include. llvm-svn: 343621
* [llvm-mca] Constify the 'notify' routines. NFC.Matt Davis2018-10-026-16/+18
| | | | | | Also fixed up some whitespace formatting in DispatchStage.cpp. llvm-svn: 343615
* [MCA] Remove SM.hasNext() call in FetchStage::execute.Owen Rodley2018-10-021-1/+1
| | | | | | | | | | | | | | | | Summary: This is redundant, as FetchStage::getNextInstruction already checks this and returns llvm::ErrorSuccess() as appropriate. NFC. Reviewers: andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D52642 llvm-svn: 343555
* [llvm-mca] Rename the 'Subtract' method to 'subtract'Matt Davis2018-10-012-2/+2
| | | | llvm-svn: 343549
* [llvm-mca] Remove redundant namespace prefixes. NFCAndrea Di Biagio2018-09-288-37/+36
| | | | | | We are already "using" namespace llvm in all the files modified by this change. llvm-svn: 343312
* [llvm-mca] Teach how to track zero registers in class RegisterFile.Andrea Di Biagio2018-09-283-26/+78
| | | | | | | | | This change is in preparation for a future work on improving support for optimizable register moves. We already know if a write is from a zero-idiom, so we can propagate that bit of information to the PRF. We use an APInt mask to identify registers that are set to zero. llvm-svn: 343307
* Test commit. NFC.Owen Rodley2018-09-281-1/+1
| | | | llvm-svn: 343296
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-272-5/+4
| | | | | | | | | | | | Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
* [llvm-mca] Improve code comments in LSUnit.{h, cpp}. NFCAndrea Di Biagio2018-09-242-15/+25
| | | | llvm-svn: 342877
* [MCA] Remove dependency on CodeGen.Dean Michael Berris2018-09-213-3/+1
| | | | | | | | | | | | | | | | | | | | | Summary: There isn't any actual dependency - there's one #include from CodeGen but nothing from the header is actually used. With this change we can use the MCA library from CodeGen without circular dependencies (e.g. for scheduling). Reviewers: andreadb Reviewed By: andreadb Authored By: orodley Subscribers: mgorny, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D52288 llvm-svn: 342706
* [TableGen][SubtargetEmitter] Add the ability for processor models to ↵Andrea Di Biagio2018-09-191-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | describe dependency breaking instructions. This patch adds the ability for processor models to describe dependency breaking instructions. Different processors may specify a different set of dependency-breaking instructions. That means, we cannot assume that all processors of the same target would use the same rules to classify dependency breaking instructions. The main goal of this patch is to provide the means to describe dependency breaking instructions directly via tablegen, and have the following TargetSubtargetInfo hooks redefined in overrides by tabegen'd XXXGenSubtargetInfo classes (here, XXX is a Target name). ``` virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const { return false; } virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const { return isZeroIdiom(MI); } ``` An instruction MI is a dependency-breaking instruction if a call to method isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to true. Similarly, an instruction MI is a special case of zero-idiom dependency breaking instruction if a call to STI.isZeroIdiom(MI) returns true. The extra APInt is used for those targets that may want to select which machine operands have their dependency broken (see comments in code). Note that by default, subtargets don't know about the existence of dependency-breaking. In the absence of external information, those method calls would always return false. A new tablegen class named STIPredicate has been added by this patch to let processor models classify instructions that have properties in common. The idea is that, a MCInstrPredicate definition can be used to "generate" an instruction equivalence class, with the idea that instructions of a same class all have a property in common. STIPredicate definitions are essentially a collection of instruction equivalence classes. Also, different processor models can specify a different variant of the same STIPredicate with different rules (i.e. predicates) to classify instructions. Tablegen backends (in this particular case, the SubtargetEmitter) will be able to process STIPredicate definitions, and automatically generate functions in XXXGenSubtargetInfo. This patch introduces two special kind of STIPredicate classes named IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a definition for those in the BtVer2 scheduling model only. This patch supersedes the one committed at r338372 (phabricator review: D49310). The main advantages are: - We can describe subtarget predicates via tablegen using STIPredicates. - We can describe zero-idioms / dep-breaking instructions directly via tablegen in the scheduling models. In future, the STIPredicates framework can be used for solving other problems. Examples of future developments are: - Teach how to identify optimizable register-register moves - Teach how to identify slow LEA instructions (each subtarget defining its own concept of "slow" LEA). - Teach how to identify instructions that have undocumented false dependencies on the output registers on some processors only. It is also (in my opinion) an elegant way to expose knowledge to both external tools like llvm-mca, and codegen passes. For example, machine schedulers in LLVM could reuse that information when internally constructing the data dependency graph for a code region. This new design feature is also an "opt-in" feature. Processor models don't have to use the new STIPredicates. It has all been designed to be as unintrusive as possible. Differential Revision: https://reviews.llvm.org/D52174 llvm-svn: 342555
* [llvm-mca] Add the ability to mark register reads/writes associated with ↵Andrea Di Biagio2018-09-186-41/+47
| | | | | | | | | | | | | | | | | | dep-breaking instructions. NFCI This patch adds two new boolean fields: - Field `ReadState::IndependentFromDef`. - Field `WriteState::WritesZero`. Field `IndependentFromDef` is set for ReadState objects associated with dependency-breaking instructions. It is used by the simulator when updating data dependencies between registers. Field `WritesZero` is set by WriteState objects associated with dependency breaking zero-idiom instructions. It helps the PRF identify which writes don't consume any physical registers. llvm-svn: 342483
* [llvm-mca] Slightly refactor class InstRef. NFC.Andrea Di Biagio2018-09-182-10/+13
| | | | llvm-svn: 342480
* Revert r342148 (and follow-on fix attempts r342154, r342180, r342182, r342193)Nico Weber2018-09-151-4/+8
| | | | | | | Many bots buildling with make have been broken for several days, e.g. http://lab.llvm.org:8011/builders/lld-x86_64-darwin13 llvm-svn: 342336
* Renovate CMake files in the `llvm-(cfi-verify|exegesis|mca)` tools.Richard Diamond2018-09-131-8/+4
| | | | llvm-svn: 342148
* [llvm-mca] Delay calculation of Cycles per Resources, separate the cycles ↵Matt Davis2018-09-1112-31/+76
| | | | | | | | | | | | | | | | | | | | | | | | | and resource quantities. Summary: This patch removes the storing of accumulated floating point data within the llvm-mca library. This patch splits-up the two quantities: cycles and number of resource units. By splitting-up these two quantities, we delay the calculation of "cycles per resource unit" until that value is read, reducing the chance of accumulating floating point error. I considered using the APFloat, but after measuring performance, for a large (many iteration) sample, I decided to go with this faster solution. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: llvm-commits, javed.absar, tschuett, gbedwell Differential Revision: https://reviews.llvm.org/D51903 llvm-svn: 341980
* [llvm-mca] Fix typo in debug output. NFC.Matt Davis2018-09-011-1/+1
| | | | llvm-svn: 341281
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