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* [PowerPC] Move test to correct location.Stefan Pintilie2018-03-071-0/+0
| | | | | | | Test was added in r326906 to an incorrect location. Moving the test to PPC CodeGen directory as the test is PPC specific. llvm-svn: 326923
* [X86] Make the MUL->VPMADDWD work before op legalization on AVX1 targets. ↵Craig Topper2018-03-071-94/+58
| | | | | | | | | | | | Simplify feature checks by using isTypeLegal. The v8i32 conversion on AVX1 targets was only working after LowerMUL splits 256-bit vectors. While I was there I've also made it so we don't have to check for AVX2 and BWI directly and instead just ask if the type is legal. Differential Revision: https://reviews.llvm.org/D44190 llvm-svn: 326917
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-074-6/+4
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [AMDGPU] Increased vector length for global/constant loads.Farhana Aleen2018-03-073-1/+71
| | | | | | | | | | | | | | | Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D44179 llvm-svn: 326910
* Re-land: Teach CorrelatedValuePropagation to reduce the width of udiv/urem ↵Justin Lebar2018-03-072-0/+196
| | | | | | | | | | | | | | | instructions. Summary: If the operands of a udiv/urem can be proved to fit within a smaller power-of-two-sized type, reduce the width of the udiv/urem. Backed out for failing an assert in clang bootstrap builds. Re-landing with a fix for handling non-power-of-two inputs (e.g. udiv i24). Original Differential Revision: https://reviews.llvm.org/D44102 llvm-svn: 326908
* Revert "[AMDGPU] Widened vector length for global/constant address space."Farhana Aleen2018-03-073-71/+1
| | | | | | This reverts commit ce988cc100dc65e7c6c727aff31ceb99231cab03. llvm-svn: 326907
* [PowerPC] LSR tunings for PowerPCStefan Pintilie2018-03-071-0/+57
| | | | | | | | | The purpose of this patch is to have LSR generate better code on Power. This is done by overriding isLSRCostLess. Differential Revision: https://reviews.llvm.org/D40855 llvm-svn: 326906
* [AMDGPU] Widened vector length for global/constant address space.Farhana Aleen2018-03-073-1/+71
| | | | llvm-svn: 326904
* [dwarfdump] Only print CU relative offset in verbose modeJonas Devlieghere2018-03-077-60/+60
| | | | | | | | | | | | Instead of only printing the CU-relative offset in non-verbose mode, it makes more sense to only printed the resolved address. In verbose mode we still print both. Differential revision: https://reviews.llvm.org/D44148 rdar://33525475 llvm-svn: 326903
* Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""Alexander Kornienko2018-03-079-84/+54
| | | | | | | | | | | | | | | | This reverts commit r326839. r326839 breaks assembly file parsing: $ cat q.c void g() {} $ clang -S q.c -g $ clang -g -c q.s q.s:9:2: error: file number already allocated .file 1 "/tmp/test" "q.c" ^ llvm-svn: 326902
* Revert rL326898: "Teach CorrelatedValuePropagation to reduce the width of ↵Justin Lebar2018-03-072-190/+0
| | | | | | | | | | udiv/urem instructions." Breaks bootstrap builds: clang built with this patch asserts while building MCDwarf.cpp: Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed. llvm-svn: 326900
* Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.Justin Lebar2018-03-072-0/+190
| | | | | | | | | | | | | | Summary: If the operands of a udiv/urem can be proved to fit within a smaller power-of-two-sized type, reduce the width of the udiv/urem. Reviewers: spatel, sanjoy Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D44102 llvm-svn: 326898
* [X86][X87] Add X87 fp80 conversion testsSimon Pilgrim2018-03-071-0/+1123
| | | | llvm-svn: 326897
* [mips] Correct the definition of m(f|t)c(0|2)Simon Dardis2018-03-0710-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | These instructions are defined as taking a GPR register and a coprocessor register for ISAs up to MIPS32. MIPS32 extended the definition to allow a selector--a value from 0 to 32--to access another register. These instructions are now internally defined as being MIPS-I instructions, but are rejected for pre-MIPS32 ISA's if they have an explicit selector which is non-zero. This deviates slightly from GAS's behaviour which rejects assembly instructions with an explicit selector for pre-MIPS32 ISAs. E.g: mfc0 $4, $5, 0 is rejected by GAS for MIPS-I to MIPS-V but will be accepted with this patch for MIPS-I to MIPS-V. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41662 llvm-svn: 326890
* [LoadStoreVectorizer] Differentiate between <1 x T> and TSven van Haastregt2018-03-071-0/+14
| | | | | | | | | | | The LoadStoreVectorizer thought that <1 x T> and T were the same types when merging stores, leading to a crash later. Patch by Erik Hogeman. Differential Revision: https://reviews.llvm.org/D44014 llvm-svn: 326884
* [ARM] Fix for PR36577Sjoerd Meijer2018-03-071-0/+28
| | | | | | | | | | | | | Don't PerformSHLSimplify if the given node is used by a node that also uses a constant because we may get stuck in an infinite combine loop. bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36577 Patch by Sam Parker. Differential Revision: https://reviews.llvm.org/D44097 llvm-svn: 326882
* Add early exit on reassociation of 0 expression.Evgeny Stupachenko2018-03-071-0/+19
| | | | | | | | | | | | | | Summary: Before the patch a try to reassociate ((v * 16) * 0) * 1 fall into infinite loop Reviewers: pankajchawla Differential Revision: http://reviews.llvm.org/D41467 From: Evgeny Stupachenko <evstupac@gmail.com> <evgeny.v.stupachenko@intel.com> llvm-svn: 326861
* Reapply "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-069-54/+84
| | | | | | | | Fixes the bug found by asan. Also XFAIL the new test for Darwin, which is stuck on DWARF v2, and fix up other tests so they stop failing on Windows. llvm-svn: 326839
* [TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorEltsSimon Pilgrim2018-03-069-648/+737
| | | | | | | | Notably helps cleanup after legalization of vector types Differential Revision: https://reviews.llvm.org/D43674 llvm-svn: 326838
* DA: remove uses of GEP, only ask SCEVSebastian Pop2018-03-0628-1025/+493
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's been quite some time the Dependence Analysis (DA) is broken, as it uses the GEP representation to "identify" multi-dimensional arrays. It even wrongly detects multi-dimensional arrays in single nested loops: from test/Analysis/DependenceAnalysis/Coupled.ll, example @couple6 ;; for (long int i = 0; i < 50; i++) { ;; A[i][3*i - 6] = i; ;; *B++ = A[i][i]; DA used to detect two subscripts, which makes no sense in the LLVM IR or in C/C++ semantics, as there are no guarantees as in Fortran of subscripts not overlapping into a next array dimension: maximum nesting levels = 1 SrcPtrSCEV = %A DstPtrSCEV = %A using GEPs subscript 0 src = {0,+,1}<nuw><nsw><%for.body> dst = {0,+,1}<nuw><nsw><%for.body> class = 1 loops = {1} subscript 1 src = {-6,+,3}<nsw><%for.body> dst = {0,+,1}<nuw><nsw><%for.body> class = 1 loops = {1} Separable = {} Coupled = {1} With the current patch, DA will correctly work on only one dimension: maximum nesting levels = 1 SrcSCEV = {(-2424 + %A)<nsw>,+,1212}<%for.body> DstSCEV = {%A,+,404}<%for.body> subscript 0 src = {(-2424 + %A)<nsw>,+,1212}<%for.body> dst = {%A,+,404}<%for.body> class = 1 loops = {1} Separable = {0} Coupled = {} This change removes all uses of GEP from DA, and we now only rely on the SCEV representation. The patch does not turn on -da-delinearize by default, and so the DA analysis will be more conservative in the case of multi-dimensional memory accesses in nested loops. I disabled some interchange tests, as the DA is not able to disambiguate the dependence anymore. To make DA stronger, we may need to compute a bound on the number of iterations based on the access functions and array dimensions. The patch cleans up all the CHECKs in test/Transforms/LoopInterchange/*.ll to avoid checking for snippets of LLVM IR: this form of checking is very hard to maintain. Instead, we now check for output of the pass that are more meaningful than dozens of lines of LLVM IR. Some tests now require -debug messages and thus only enabled with asserts. Patch written by Sebastian Pop and Aditya Kumar. Differential Revision: https://reviews.llvm.org/D35430 llvm-svn: 326837
* [SymboleFilePDB] Put the test input back that my previous commit clobberedAaron Smith2018-03-061-0/+0
| | | | llvm-svn: 326831
* [Hexagon] Update more testcasesKrzysztof Parzyszek2018-03-0634-112/+103
| | | | llvm-svn: 326830
* [Hexagon] Remove {{ *}} from testcasesKrzysztof Parzyszek2018-03-0630-198/+197
| | | | | | The spaces in the instructions are now consistent. llvm-svn: 326829
* [X86] Reject registers that require a REX prefix in inline asm constraints ↵Craig Topper2018-03-062-2/+23
| | | | | | | | | | in 32-bit mode We don't currently reject r8-r15 or xmm8-32 or bpl/spl/sil/dil in 32-bit mode. Differential Revision: https://reviews.llvm.org/D44031 llvm-svn: 326826
* [AMDGPU] Add default ISA version targetsStanislav Mekhanoshin2018-03-061-0/+6
| | | | | | | | | | | In case if -mattr used to modify feature set bits in llvm-mc call getIsaVersion can fail to identify specific ISA due to test mismatch. Adding default fallback tests which will always correctly report at least major version. Differential Revision: https://reviews.llvm.org/D44163 llvm-svn: 326825
* [CodeView] Emit UdtSourceLine information for enumsAaron Smith2018-03-062-1/+12
| | | | | | | | | | | | | | | | | Summary: - Emit UdtSourceLine information for enums to match MSVC - Add a method to add UDTSrcLine and call it for all Class/Struct/Union/Enum - Update test cases to verify the changes Reviewers: zturner, llvm-commits, rnk Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D44116 llvm-svn: 326824
* [PatternMatch] define m_Not using m_Xor and cst_pred_tySanjay Patel2018-03-062-14/+7
| | | | | | | | | | | | | Using cst_pred_ty in the definition allows us to match vectors with undef elements. This is a continuation of an effort to make all pattern matchers allow undef elements in vectors: rL325437 rL325466 D43792 Differential Revision: https://reviews.llvm.org/D44076 llvm-svn: 326823
* Refactor check for dllimport in the Verifier.Rafael Espindola2018-03-061-2/+0
| | | | | | This avoids duplicated code and now also rejects dllimport aliases. llvm-svn: 326814
* [AArch64] define isExtractSubvectorCheapSebastian Pop2018-03-063-21/+4
| | | | | | | | | | | | | | | | | | Following the ARM-neon backend, define isExtractSubvectorCheap to return true when extracting low and high part of a neon register. The patch disables a test in llvm/test/CodeGen/AArch64/arm64-ext.ll This testcase is fragile in the sense that it requires a BUILD_VECTOR to "survive" all DAG transforms until ISelLowering. The testcase is supposed to check that AArch64TargetLowering::ReconstructShuffle() works, and for that we need a BUILD_VECTOR in ISelLowering. As we now transform the BUILD_VECTOR earlier into an VEXT + vector_shuffle, we don't have the BUILD_VECTOR pattern when we get to ISelLowering. As there is no way to disable the combiner to only exercise the code in ISelLowering, the patch disables the testcase. Differential revision: https://reviews.llvm.org/D43973 llvm-svn: 326811
* [AMDGPU] Fix lowering OpenCL enqueue_kernelYaxun Liu2018-03-061-49/+44
| | | | | | | | | | One addrspacecast disappeared in clang emitted IR for block invoke function due to adoption of the new addr space mapping. Differential Revision: https://reviews.llvm.org/D43785 llvm-svn: 326806
* [ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath2018-03-062-4/+10
| | | | | | | | | | | | | | | This patch handling: Enable parsing of raw encodings of system registers . Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing. Disassemble msr/mrs with unpredictable sysregs as SoftFail. Fix regression due to SoftFailing some encodings. Patch by Chris Ryder Differential revision:https://reviews.llvm.org/D43374 llvm-svn: 326803
* [CallSiteSplitting] Do not crash when BB's terminator changes.Florian Hahn2018-03-061-0/+90
| | | | | | | | | | | | | | | Change doCallSiteSplitting to iterate until we reach the terminator instruction. tryToSplitCallSite can replace BB's terminator in case BB is a successor of itself. Then IE will be invalidated and we also have to check the current terminator. Reviewers: junbuml, davidxl, davide, fhahn Reviewed By: fhahn, junbuml Differential Revision: https://reviews.llvm.org/D43824 llvm-svn: 326793
* TableGen: Add !foldl operationNicolai Haehnle2018-03-061-0/+71
| | | | | Change-Id: I63d67bf6e0b315e2d3360e47e3b62c9517f38987 llvm-svn: 326790
* TableGen: Delay instantiating inline anonymous recordsNicolai Haehnle2018-03-061-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Only instantiate anonymous records once all variable references in template arguments have been resolved. This allows patterns like the new test case, which in practice can appear in expressions like: class IntrinsicTypeProfile<list<LLVMType> ty, int shift> { list<LLVMType> types = !listconcat(ty, [llvm_any_ty, LLVMMatchType<shift>]); } class FooIntrinsic<IntrinsicTypeProfile P, ...> : Intrinsic<..., P.types, ...>; Without this change, the anonymous LLVMMatchType instantiation would never get resolved. Another consequence of this change is that anonymous inline instantiations are uniqued via the folding set of the newly introduced VarDefInit. Change-Id: I7a7041a20e297cf98c9109b28d85e64e176c932a Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D43756 llvm-svn: 326788
* TableGen: Explicitly check whether a record has been resolvedNicolai Haehnle2018-03-062-12/+2
| | | | | | | | | | | | | | | | | | Summary: There are various places where resolving and constant folds can get stuck, especially around casts. We don't always signal an error for those, because in many cases they can legitimately occur without being an error in the "untaken branch" of an !if. Change-Id: I3befc0e4234c8e6cc61190504702918c9f29ce5c Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D43754 llvm-svn: 326786
* TableGen: Allow !cast of records, cleanup conversion machineryNicolai Haehnle2018-03-064-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Distinguish two relationships between types: is-a and convertible-to. For example, a bit is not an int or vice versa, but they can be converted into each other (with range checks that you can think of as "dynamic": unlike other type checks, those range checks do not happen during parsing, but only once the final values have been established). Actually converting initializers between types is subtle: even when values of type A can be converted to type B (e.g. int into string), it may not be possible to do so with a concrete initializer (e.g., a VarInit that refers to a variable of type int cannot be immediately converted to a string). For this reason, distinguish between getCastTo and convertInitializerTo: the latter implements the actual conversion when appropriate, while the former will first try to do the actual conversion and fall back to introducing a !cast operation so that the conversion will be delayed until variable references have been resolved. To make the approach of adding !cast operations to work, !cast needs to fallback to convertInitializerTo when the special string <-> record logic does not apply. This enables casting records to a subclass, although that new functionality is only truly useful together with !isa, which will be added in a later change. The test is removed because it uses !srl on a bit sequence, which cannot really be supported consistently, but luckily isn't used anywhere either. Change-Id: I98168bf52649176654ed2ec61a29bdb29970cfe7 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D43753 llvm-svn: 326785
* TableGen: Simplify BitsInit::resolveReferencesNicolai Haehnle2018-03-061-1/+30
| | | | | | | | | | | | | | | | | | | | Summary: No functional change intended. The removed code has a loop for recursive resolving, which is superseded by the recursive resolving done by the Resolver implementations. Add a test case which was broken by an earlier version of this change. Change-Id: Ib208d037b77a8bbb725977f1388601fc984723d8 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D43655 llvm-svn: 326784
* TableGen: Generalize record types to fix typeIsConvertibleTo et al.Nicolai Haehnle2018-03-062-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Allow RecordRecTy to represent the type "subclass of N superclasses", where N may be zero. Furthermore, generate RecordRecTy instances only with actual classes in the list. Keeping track of multiple superclasses is required to resolve the type of a list correctly in some cases. The old code relied on the incorrect behavior of typeIsConvertibleTo, and an earlier version of this change relied on a modified ordering of superclasses (it was committed in r325884 and then reverted because unfortunately some of clang-tblgen's backends depend on the ordering). Previously, the DefInit for each Record would have a RecordRecTy of that Record as its type. Now, all defs with the same superclasses will share the same type. This allows us to be more consistent about type checks involving records: - typeIsConvertibleTo actually requires the LHS to be a subtype of the RHS - resolveTypes will return the least supertype of given record types in all cases - different record types in the two branches of an !if are handled correctly Add a test that used to be accepted without flagging the obvious type error. Change-Id: Ib366db1a4e6a079f1a0851e469b402cddae76714 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D43680 llvm-svn: 326783
* [AVR] Remove the earlyclobber flag from LDDWRdYQDylan McKay2018-03-061-0/+139
| | | | | | | | | | | | | | | | | Before I started maintaining the AVR backend, this instruction never originally used to have an earlyclobber flag. Some time afterwards (years ago), I must've added it back in, not realising that it was left out for a reason. This pseudo instrction exists solely to work around a long standing bug in the register allocator. Before this commit, the LDDWRdYQ pseudo was not actually working around any bug. With the earlyclobber flag removed again, the LDDWRdYQ pseudo now correctly works around PR13375 again. llvm-svn: 326774
* [DebugInfo] Discard invalid DBG_VALUE instructions in LiveDebugVariablesBjorn Pettersson2018-03-062-3/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is a workaround for pr36417 https://bugs.llvm.org/show_bug.cgi?id=36417 LiveDebugVariables will now verify that the DBG_VALUE instructions are sane (prior to register allocation) by asking LIS if a virtual register used in the DBG_VALUE is live (or dead def) in the slot index before the DBG_VALUE. If it isn't sane the DBG_VALUE is discarded. One pass that was identified as introducing non-sane DBG_VALUE instructtons, when analysing pr36417, was the DAG->DAG Instruction Selection. It sometimes inserts DBG_VALUE instructions referring to a virtual register that is defined later in the same basic block. So it is a use before def kind of problem. The DBG_VALUE is typically inserted in the beginning of a basic block when this happens. The problem can be seen in the test case test/DebugInfo/X86/dbg-value-inlined-parameter.ll Reviewers: aprantl, rnk, probinson Reviewed By: aprantl Subscribers: vsk, davide, alexcrichton, Ka-Ka, eraman, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D43956 llvm-svn: 326769
* [X86] Handle EAX being live when calling chkstk for x86_64Martin Storsjo2018-03-061-0/+36
| | | | | | | | | | | | EAX can turn out to be alive here, when shrink wrapping is done (which is allowed when using dwarf exceptions, contrary to the normal case with WinCFI). This fixes PR36487. Differential Revision: https://reviews.llvm.org/D43968 llvm-svn: 326764
* Revert "[DWARFv5] Emit file 0 to the line table."Paul Robinson2018-03-069-84/+56
| | | | | | | | | Caused an asan failure. This reverts commit d54883f081186cdcce74e6f98cfc0438579ec019. aka r326758 llvm-svn: 326762
* [DWARFv5] Emit file 0 to the line table.Paul Robinson2018-03-069-56/+84
| | | | | | | | | | | DWARF v5 specifies that the root file (also given in the DW_AT_name attribute of the compilation unit DIE) should be emitted explicitly to the line table's list of files. This makes the line table more independent of the .debug_info section. Differential Revision: https://reviews.llvm.org/D44054 llvm-svn: 326758
* Disable llvm-opt-fuzzer/exec-options.ll on Windows, it is too flakyReid Kleckner2018-03-051-0/+6
| | | | llvm-svn: 326752
* GlobalISel: IRTranslate llvm.fabs.* intrinsicVolkan Keles2018-03-051-0/+11
| | | | | | | | | | | | | | | | Summary: Fabs is a common floating-point operation, especially for some expansions. This patch adds a new generic opcode for llvm.fabs.* intrinsic in order to avoid building/matching this intrinsic. Reviewers: qcolombet, aditya_nandakumar, dsanders, rovka Reviewed By: aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D43864 llvm-svn: 326749
* [RewriteStatepoints] Fix stale parse pointsDaniel Neilson2018-03-053-10/+52
| | | | | | | | | | | | | | | | | | | | | | | | Summary: RewriteStatepointsForGC collects parse points for further processing. During the collection if a callsite is found in an unreachable block (DominatorTree::isReachableFromEntry()) then all unreachable blocks are removed by removeUnreachableBlocks(). Some of the removed blocks could have been reachable according to DominatorTree::isReachableFromEntry(). In this case the collected parse points became stale and resulted in a crash when accessed. The fix is to unconditionally canonicalize the IR to removeUnreachableBlocks and then collect the parse points. The added test crashes with the old version and passes with this patch. Patch by Yevgeny Rouban! Reviewed by: Anna Differential Revision: https://reviews.llvm.org/D43929 llvm-svn: 326748
* [X86] Add silvermont fp arithmetic cost model testsSimon Pilgrim2018-03-051-0/+73
| | | | | | Add silvermont to existing high coverage tests instead of repeating in slm-arith-costs.ll llvm-svn: 326747
* [AVR] Fix the test suite after r326500.Dylan McKay2018-03-051-1/+1
| | | | | | r326500 subtly changed the way the instructions are printed. llvm-svn: 326742
* [SLP] Additional tests for stores vectorization, NFC.Alexey Bataev2018-03-051-0/+179
| | | | llvm-svn: 326740
* [PowerPC] Do not emit record-form rotates when record-form andi sufficesNemanja Ivanovic2018-03-052-1/+43
| | | | | | | | | | | | | | | | Up until Power9, the performance profile for rlwinm., rldicl. and andi. looked more or less equivalent. However with Power9, the rotates are still 2-way cracked whereas the and-immediate is not. This patch just ensures that we don't emit record-form rotates when an andi. is adequate. As first pointed out by Carrot in https://bugs.llvm.org/show_bug.cgi?id=30833 (this patch is a fix for that PR). Differential Revision: https://reviews.llvm.org/D43977 llvm-svn: 326736
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