diff options
| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-07 17:27:18 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-07 17:27:18 +0000 |
| commit | 2c3edf05679e3c8cf341b2d1b2f517533cdae6e3 (patch) | |
| tree | 4e14a8b018884f4da92a33f09b8fdf6875fae9a9 /llvm/test | |
| parent | b0084a0eee27527981130bdc85d1810082fabf00 (diff) | |
| download | bcm5719-llvm-2c3edf05679e3c8cf341b2d1b2f517533cdae6e3.tar.gz bcm5719-llvm-2c3edf05679e3c8cf341b2d1b2f517533cdae6e3.zip | |
[Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones
This is a follow-up to r325169, this time for all types, not just HVX
vector types.
Disable this by default, since it's not always safe.
llvm-svn: 326915
Diffstat (limited to 'llvm/test')
4 files changed, 4 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll index 5494bd84fcc..ca1c1747013 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-packetizer < %s | FileCheck %s +; RUN: llc -march=hexagon -disable-packetizer -hexagon-align-loads < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0) diff --git a/llvm/test/CodeGen/Hexagon/select-instr-align.ll b/llvm/test/CodeGen/Hexagon/select-instr-align.ll index 9d8939282c6..1021f924f1d 100644 --- a/llvm/test/CodeGen/Hexagon/select-instr-align.ll +++ b/llvm/test/CodeGen/Hexagon/select-instr-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hvx-expand-unaligned-loads=0 < %s | FileCheck %s +; RUN: llc -march=hexagon -hexagon-align-loads=0 < %s | FileCheck %s ; CHECK-LABEL: aligned_load: ; CHECK: = vmem({{.*}}) diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll index 32abb75f20f..546ffdd66ff 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -march=hexagon -O0 -hexagon-align-loads=0 < %s | FileCheck %s ; CHECK-LABEL: danny: ; CHECK-DAG: [[T0:r[0-9]+]] = memuh(r0+#0) diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll index f49a1e24a1b..83d56ed9ed4 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll @@ -1,9 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s ; Check that store is post-incremented. -; CHECK: memuh(r{{[0-9]+}}+#6) -; CHECK: combine(r{{[0-9]+}},r{{[0-9]+}}) -; CHECK: vaddh +; CHECK: memh(r{{[0-9]+}}++#2) target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" |
