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* ARM: mark various aliases with their architecture requirements.Tim Northover2013-10-242-0/+24
| | | | | | | | | | If an alias inherits directly from InstAlias then it doesn't get any default "Requires" values, so llvm-mc will allow it even on architectures that don't support the underlying instruction. This tidies up the obvious VFP and NEON cases I found. llvm-svn: 193340
* Added tests for microMIPS relocations 1.Zoran Jovanovic2013-10-243-0/+191
| | | | llvm-svn: 193332
* ARM: Use non-VFP softcalls on embedded Darwinish targetsTim Northover2013-10-241-0/+22
| | | | | | | | | | | | | The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1 code to make use of VFP instructions by switching back to ARM mode, they make no sense for M-class processors which don't even have an ARM mode. Given that justification, in practice this is a platform ABI decision so the actual check is based on that rather than CPU features. rdar://problem/15302004 llvm-svn: 193327
* ARM: fix assert on unpredictable POP instruction.Tim Northover2013-10-242-5/+7
| | | | | | | | | | | POP instructions are aliased to the ARM LDM variants but have different syntax. This caused two problems: we tried to access a non-existent operand to annotate the '!', and the error message didn't make much sense. With some vigorous hand-waving in the error message both problems can be fixed. llvm-svn: 193322
* Added test for -elf configuration, to see that _alloca call is properly Yaron Keren2013-10-241-9/+16
| | | | | | | | generated. See: http://llvm.org/viewvc/llvm-project?view=revision&revision=193289 llvm-svn: 193321
* Make sure SP is always aligned on a 2 byte boundaryJob Noorman2013-10-241-0/+17
| | | | llvm-svn: 193320
* fix PR17635: false positive with packed structuresNuno Lopes2013-10-241-0/+29
| | | | | | LLVM optimizers may widen accesses to packed structures that overflow the structure itself, but should be in bounds up to the alignment of the object llvm-svn: 193317
* [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.Amara Emerson2013-10-241-0/+17
| | | | | | | | | When generating the IfTrue basic block during the F128CSEL pseudo-instruction handling, the NZCV live-in for the newly created BB wasn't being added. This caused a fault during MI-sched/live range calculation when the predecessor for the fall-through BB didn't have a live-in for phys-reg as expected. llvm-svn: 193316
* AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsicsElena Demikhovsky2013-10-241-0/+15
| | | | llvm-svn: 193312
* Replace sse41/sse42 with sse4.1/sse4.2 in test command lines to fix bots.Craig Topper2013-10-242-2/+2
| | | | llvm-svn: 193311
* Add non-AVX tests for AES intrinsics.Craig Topper2013-10-241-0/+48
| | | | llvm-svn: 193310
* Add tests for SSE intrinsics in non-avx mode by copying from the AVX test ↵Craig Topper2013-10-246-0/+1704
| | | | | | cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally. llvm-svn: 193309
* Fix a bug in LinearFunctionTestReplace that created invalid loop exit checks.Juergen Ributzka2013-10-241-0/+26
| | | | | | Reviewed by Andy llvm-svn: 193303
* X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate.Benjamin Kramer2013-10-235-4/+44
| | | | | | Also update the cost model. llvm-svn: 193270
* X86: Custom lower zext v16i8 to v16i16.Benjamin Kramer2013-10-232-0/+21
| | | | | | | | | | | | | | | | | On sandy bridge (PR17654) we now get vpxor %xmm1, %xmm1, %xmm1 vpunpckhbw %xmm1, %xmm0, %xmm2 vpunpcklbw %xmm1, %xmm0, %xmm0 vinsertf128 $1, %xmm2, %ymm0, %ymm0 On haswell it's a simple vpmovzxbw %xmm0, %ymm0 There is a maze of duplicated and dead transforms and patterns in this area. Remove the dead custom lowering of zext v8i16 to v8i32, that's already handled by LowerAVXExtend. llvm-svn: 193262
* Fix PR17631Michael Liao2013-10-231-0/+22
| | | | | | | | | - Skip instructions added in prolog. For specific targets, prolog may insert helper function calls (e.g. _chkstk will be called when there're more than 4K bytes allocated on stack). However, these helpers don't use/def YMM/XMM registers. llvm-svn: 193261
* Add llvm-c-test to check-llvm.NAKAMURA Takumi2013-10-231-4/+1
| | | | llvm-svn: 193258
* Use address-taken to disambiguate global variable and indirect memops.Shuxin Yang2013-10-237-9/+38
| | | | | | | | | | Major steps include: 1). introduces a not-addr-taken bit-field in GlobalVariable 2). GlobalOpt pass sets "not-address-taken" if it proves a global varirable dosen't have its address taken. 3). AA use this info for disambiguation. llvm-svn: 193251
* Fix cmake dependency on llvm-c-test in testAnders Waldenborg2013-10-231-0/+4
| | | | llvm-svn: 193243
* [mips][msa] Direct Object Emission support for the LSA instruction.Matheus Almeida2013-10-231-0/+9
| | | | llvm-svn: 193240
* [mips][msa] Added support for matching fexp2 from normal IR (i.e. not ↵Daniel Sanders2013-10-231-0/+69
| | | | | | intrinsics) llvm-svn: 193239
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-235-4/+34
| | | | llvm-svn: 193238
* Fix check for supported targets in llvm-c lit.local.cfgAnders Waldenborg2013-10-231-1/+3
| | | | llvm-svn: 193235
* Add llvm-c-test tool for testing llvm-cAnders Waldenborg2013-10-236-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides rudimentary testing of the llvm-c api. The following commands are implemented: * --module-dump Read bytecode from stdin - print ir * --module-list-functions Read bytecode from stdin - list summary of functions * --module-list-globals Read bytecode from stdin - list summary of globals * --targets-list List available targets * --object-list-sections Read object file from stdin - list sections * --object-list-symbols Read object file from stdin - list symbols (like nm) * --disassemble Read lines of triple, hex ascii machine code from stdin - print disassembly * --calc Read lines of name, rpn from stdin - print generated module ir Differential-Revision: http://llvm-reviews.chandlerc.com/D1776 llvm-svn: 193233
* R600/SI: fix MIMG writemask adjustementTom Stellard2013-10-231-0/+93
| | | | | | | | | | | | This fixes piglit: - shaders/glsl-fs-texture2d-masked - shaders/glsl-fs-texture2d-masked-4 Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 193222
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-235-115/+502
| | | | | | | | | | The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. llvm-svn: 193215
* R600/SI: Add support for i64 bitwise orTom Stellard2013-10-231-4/+17
| | | | llvm-svn: 193213
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-231-5/+10
| | | | llvm-svn: 193212
* MC: Support multiple sections with the same name in the same comdat groupDavid Blaikie2013-10-221-0/+41
| | | | | | Code review by Eric Christopher and Rafael Espindola. llvm-svn: 193209
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-223-0/+39
| | | | | | | | | | | | | | The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 llvm-svn: 193185
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-0/+39
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. llvm-svn: 193179
* Simplify testing case (Thanks Rafael for the testing case).Manman Ren2013-10-221-28/+22
| | | | llvm-svn: 193177
* [mips][msa] Direct Object Emission support for conditional branches.Matheus Almeida2013-10-221-0/+78
| | | | | | | | | | | | These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
* AVX-512: aligned / unaligned load and store for 512-bit integer vectors.Elena Demikhovsky2013-10-221-0/+28
| | | | llvm-svn: 193156
* Add testcase for PR3168. It was fixed over time.Bill Wendling2013-10-221-0/+21
| | | | | | PR3168 llvm-svn: 193152
* TBAA: fix PR17620.Manman Ren2013-10-221-0/+51
| | | | | | | We can have a struct type with a single field and the field does not start with 0. In that case, we should correctly update the offset. llvm-svn: 193137
* Fix spelling, grammar, and match naming convention for test files.Eric Christopher2013-10-211-1/+1
| | | | llvm-svn: 193130
* [AArch64] Add the constraint to NEON scalar mla/mls instructions.Chad Rosier2013-10-211-20/+24
| | | | llvm-svn: 193117
* SimplifyCFG: Don't duplicate calls to functions marked noduplicate v2Tom Stellard2013-10-211-0/+37
| | | | | | | v2: - Use CI->cannotDuplicate() llvm-svn: 193115
* Fix CodeGen for vectors of pointers with address spaces.Matt Arsenault2013-10-211-0/+30
| | | | llvm-svn: 193112
* Fix CodeGen for different size address space GEPsMatt Arsenault2013-10-211-0/+10
| | | | llvm-svn: 193111
* Teach SimplifyCFG about address spacesMatt Arsenault2013-10-212-11/+104
| | | | llvm-svn: 193104
* Fix creating bitcasts between address spaces in SCEV.Matt Arsenault2013-10-211-1/+27
| | | | | | | | The test before wasn't successfully testing this since it was missing the datalayout piece to change the size of the second address space. llvm-svn: 193102
* X86 vector element shift-by-immediate instructions take i8 immediates. MakeLang Hames2013-10-212-4/+4
| | | | | | | | | | | | | | the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes <rdar://problem/14968098> llvm-svn: 193096
* Optimize more linkonce_odr values during LTO.Rafael Espindola2013-10-212-3/+12
| | | | | | | | | | | When a linkonce_odr value that is on the dso list is not unnamed_addr we can still look to see if anything is actually using its address. If not, it is safe to hide it. This patch implements that by moving GlobalStatus to Transforms/Utils and using it in Internalize. llvm-svn: 193090
* DebugInfo: Hash DW_FORM_GNU_str_index as a string.David Blaikie2013-10-211-2/+2
| | | | | | | | | | Found while adding type safety to the various DWARF enumerations (form, attribute, tag, etc) that caused Clang to warn on an incompletely covered switch. Converting the comment to a default/unreachable uncovered this case of an unsupported form encoding. Seems we were skipping fission strings entirely. llvm-svn: 193089
* AVX-512: MUL operation lowering for v8i64Elena Demikhovsky2013-10-211-1/+10
| | | | llvm-svn: 193083
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-211-0/+30
| | | | llvm-svn: 193082
* [mips][msa] Direct Object Emission support for LDI instructions.Matheus Almeida2013-10-211-0/+19
| | | | llvm-svn: 193081
* [mips][msa] Direct Object Emission support for MOVE.v.Matheus Almeida2013-10-211-0/+3
| | | | llvm-svn: 193080
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