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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-10-23 00:44:19 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-10-23 00:44:19 +0000 |
| commit | fb9616905a663d8b5e4ab3b7afacfb0f04476264 (patch) | |
| tree | 2a0a53504521e7cd2366a5194cd28c5fffed2402 /llvm/test | |
| parent | a66cafa096184af93b4f0250ef8ff61c85b0043d (diff) | |
| download | bcm5719-llvm-fb9616905a663d8b5e4ab3b7afacfb0f04476264.tar.gz bcm5719-llvm-fb9616905a663d8b5e4ab3b7afacfb0f04476264.zip | |
R600/SI: Add support for i64 bitwise or
llvm-svn: 193213
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/R600/or.ll | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/R600/or.ll b/llvm/test/CodeGen/R600/or.ll index 3db892a3624..6950ed0dfb5 100644 --- a/llvm/test/CodeGen/R600/or.ll +++ b/llvm/test/CodeGen/R600/or.ll @@ -1,11 +1,11 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; EG-CHECK: @or_v2i32 +; EG-CHECK-LABEL: @or_v2i32 ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @or_v2i32 +;SI-CHECK-LABEL: @or_v2i32 ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} @@ -18,13 +18,13 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) ret void } -; EG-CHECK: @or_v4i32 +; EG-CHECK-LABEL: @or_v4i32 ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @or_v4i32 +;SI-CHECK-LABEL: @or_v4i32 ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} @@ -38,3 +38,16 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +; EG-CHECK-LABEL: @or_i64 +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[3].X +; SI-CHECK-LABEL: @or_i64 +; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}} +; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}} +define void @or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = or i64 %a, %b + store i64 %0, i64 addrspace(1)* %out + ret void +} |
