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* [IR] Allow attributes with global variablesJaved Absar2017-05-112-0/+38
| | | | | | | | | | | | | This patch extends llvm-ir to allow attributes to be set on global variables. An RFC was sent out earlier by my colleague James Molloy: http://lists.llvm.org/pipermail/cfe-dev/2017-March/053100.html A key part of that proposal was to extend LLVM-IR to carry attributes on global variables. This generic feature could be useful for multiple purposes. In our present context, it would be useful to carry user specified sections for bss/rodata/data. Reviewed by: Jonathan Roelofs, Reid Kleckner Differential Revision: https://reviews.llvm.org/D32009 llvm-svn: 302794
* [msan] Fix PR32842Alexander Potapenko2017-05-111-0/+20
| | | | | | | | | | | | | | | | | | | | It turned out that MSan was incorrectly calculating the shadow for int comparisons: it was done by truncating the result of (Shadow1 OR Shadow2) to i1, effectively rendering all bits except LSB useless. This approach doesn't work e.g. in the case where the values being compared are even (i.e. have the LSB of the shadow equal to zero). Instead, if CreateShadowCast() has to cast a bigger int to i1, we replace the truncation with an ICMP to 0. This patch doesn't affect the code generated for SPEC 2006 binaries, i.e. there's no performance impact. For the test case reported in PR32842 MSan with the patch generates a slightly more efficient code: orq %rcx, %rax jne .LBB0_6 , instead of: orl %ecx, %eax testb $1, %al jne .LBB0_6 llvm-svn: 302787
* [x86] Fix a failure to select with AVX-512 when the type legalizerChandler Carruth2017-05-111-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | manages to form a VSELECT with a non-i1 element type condition. Those are technically allowed in SDAG (at least, the generic type legalization logic will form them and I wouldn't want to try to audit everything te preclude forming them) so we need to be able to lower them. This isn't too hard to implement. We mark VSELECT as custom so we get a chance in C++, add a fast path for i1 conditions to get directly handled by the patterns, and a fallback when we need to manually force the condition to be an i1 that uses the vptestm instruction to turn a non-mask into a mask. This, unsurprisingly, generates awful code. But it at least doesn't crash. This was actually impacting open source packages built with LLVM for AVX-512 in the wild, so quickly landing a patch that at least stops the immediate bleeding. I think I've found where to fix the codegen quality issue, but less confident of that change so separating it out from the thing that doesn't change the result of any existing test case but causes mine to not crash. llvm-svn: 302785
* [ARM][GlobalISel] Legalize narrow scalar ops by wideningDiana Picus2017-05-113-54/+213
| | | | | | | | | | | | | | This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
* [ARM][GlobalISel] Support for G_ANYEXTDiana Picus2017-05-112-0/+99
| | | | | | | | | | | | | | G_ANYEXT can be introduced by the legalizer when widening scalars. Add support for it in the register bank info (same mapping as everything else) and in the instruction selector. When selecting it, we treat it as a COPY, just like G_TRUNC. On this occasion we get rid of some assertions in selectCopy so we can reuse it. This shouldn't be a problem at the moment since we're not supporting any complicated cases (e.g. FPR, different register banks). We might want to separate the paths when we do. llvm-svn: 302778
* [GlobalISel][X86] G_ICMP support.Igor Breger2017-05-114-5/+1021
| | | | | | | | | | | | | | Summary: support G_ICMP for scalar types i8/i16/i64. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits, krytarowski Differential Revision: https://reviews.llvm.org/D32995 llvm-svn: 302774
* Revert "[SDAG] Relax conditions under stores of loaded values can be merged"David L. Jones2017-05-101-10/+18
| | | | | | | | | | | | | | | | | | | | | This reverts r302712. The change fails with ASAN enabled: ERROR: AddressSanitizer: use-after-poison on address ... at ... READ of size 2 at ... thread T0 #0 ... in llvm::SDNode::getNumValues() const <snip>/include/llvm/CodeGen/SelectionDAGNodes.h:855:42 #1 ... in llvm::SDNode::hasAnyUseOfValue(unsigned int) const <snip>/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7270:3 #2 ... in llvm::SDValue::use_empty() const <snip> include/llvm/CodeGen/SelectionDAGNodes.h:1042:17 #3 ... in (anonymous namespace)::DAGCombiner::MergeConsecutiveStores(llvm::StoreSDNode*) <snip>/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12944:7 Reviewers: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33081 llvm-svn: 302746
* [InstCombine] remove fold that swaps xor/or with constants; NFCISanjay Patel2017-05-101-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2) This canonicalization was added at: https://reviews.llvm.org/rL7264 By moving xors out/down, we can more easily combine constants. I'm adding tests that do not change with this patch, so we can verify that those kinds of transforms are still happening. This is no-functional-change-intended because there's a later fold: // (X^C)|Y -> (X|Y)^C iff Y&C == 0 ...and demanded-bits appears to guarantee that any fold that would have hit the fold we're removing here would be caught by that 2nd fold. Similar reasoning was used in: https://reviews.llvm.org/rL299384 The larger motivation for removing this code is that it could interfere with the fix for PR32706: https://bugs.llvm.org/show_bug.cgi?id=32706 Ie, we're not checking if the 'xor' is actually a 'not', so we could reverse a 'not' optimization and cause an infinite loop by altering an 'xor X, -1'. Differential Revision: https://reviews.llvm.org/D33050 llvm-svn: 302733
* AMDGPU: Make some packed shuffles freeMatt Arsenault2017-05-103-41/+119
| | | | | | | VOP3P instructions can encode access to either half of the register. llvm-svn: 302730
* [SDAG] Relax conditions under stores of loaded values can be mergedNirav Dave2017-05-101-18/+10
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Allow consecutive stores whose values come from consecutive loads to merged in the presense of other uses of the loads. Previously this was disallowed as in general the merged load cannot be shared with the other uses. Merging N stores into 1 may cause as many as N redundant loads. However in the context of caching this should have neglible affect on memory pressure and reduce instruction count making it almost always a win. Fixes PR32086. Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30471 llvm-svn: 302712
* [InstSimplify, InstCombine] move 'or' simplification tests; NFCSanjay Patel2017-05-103-181/+181
| | | | | | | Surprisingly, I don't think these are redundant for InstSimplify. They were just misplaced as InstCombine tests. llvm-svn: 302684
* [X86][SSE] Check vec_set BUILD_VECTOR tests on both 32 and 64-bit targetsSimon Pilgrim2017-05-1010-99/+204
| | | | llvm-svn: 302683
* [AArch64][RegisterBankInfo] Change the default mapping of fp stores.Quentin Colombet2017-05-101-0/+46
| | | | | | | | For stores, check if the stored value is defined by a floating point instruction and if yes, we return a default mapping with FPR instead of GPR. llvm-svn: 302679
* [AArch64] Enable use of reduction intrinsics.Amara Emerson2017-05-105-481/+114
| | | | | | | | | | | | | | The new experimental reduction intrinsics can now be used, so I'm enabling this for AArch64. We will need this for SVE anyway, so it makes sense to do this for NEON reductions as well. The existing code to match shufflevector patterns are replaced with a direct lowering of the reductions to AArch64-specific nodes. Tests updated with the new, simpler, representation. Differential Revision: https://reviews.llvm.org/D32247 llvm-svn: 302678
* [InstCombine] remove redundant testsSanjay Patel2017-05-101-34/+0
| | | | | | | | | | | The first test in this file is duplicated exactly in and.ll -> test33. We have commuted and vector variants there too. The second test is a composite of 2 folds. The first fold is tested independently in add.ll -> flip_and_mask (including vector variant). After that transform fires, the IR is identical to the first transform. llvm-svn: 302676
* [InstCombine] fix auto-generated FileCheck-captured variable refsSanjay Patel2017-05-103-6/+6
| | | | | | | The script at utils/update_test_checks.py has (had?) a bug when variables start with the same sequence of letters (clearly, not all of the time). llvm-svn: 302674
* [InstCombine] fix typo in test comment; NFCSanjay Patel2017-05-101-1/+1
| | | | llvm-svn: 302669
* [SystemZ] Add miscellaneous instructionsUlrich Weigand2017-05-103-0/+261
| | | | | | | | This adds a few missing instructions for the assembler and disassembler. Those should be the last missing general- purpose (Chapter 7) instructions for the z10 ISA. llvm-svn: 302667
* [SystemZ] Add missing arithmetic instructionsUlrich Weigand2017-05-103-0/+1451
| | | | | | | | | This adds the remaining general arithmetic instructions for assembler / disassembler use. Most of these are not useful for codegen; a few might be, and those are listed in the README.txt for future improvements. llvm-svn: 302665
* [llvm-readobj] Improve errors on invalid binarySam Clegg2017-05-102-2/+9
| | | | | | | | | | | | | | The previous code was discarding the error message from createBinary() by calling errorToErrorCode(). This meant that such error were always reported unhelpfully as "Invalid data was encountered while parsing the file". Other tools such as llvm-objdump already produce a more the error message in this case. Differential Revision: https://reviews.llvm.org/D32985 llvm-svn: 302664
* [InstCombine] add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1Sanjay Patel2017-05-101-6/+4
| | | | | | | | | | | | | | This is another step towards favoring 'not' ops over random 'xor' in IR: https://bugs.llvm.org/show_bug.cgi?id=32706 This transformation may have occurred in longer IR sequences using computeKnownBits, but that could be much more expensive to calculate. As the scalar result shows, we do not currently favor 'not' in all cases. The 'not' created by the transform is transformed again (unnecessarily). Vectors don't have this problem because vectors are (wrongly) excluded from several other combines. llvm-svn: 302659
* [LLVM][inline-asm] Altmacro string escape character '!'Michael Zuckerman2017-05-101-0/+29
| | | | | | | | | | | | | This patch is the fourth patch in a series of reviews for the Altmacro feature. This patch introduces a new escape character '!' and it depends on D32701. according to https://sourceware.org/binutils/docs/as/Altmacro.html: "single-character string escape To include any single character literally in a string (even if the character would otherwise have some special meaning), you can prefix the character with !' (an exclamation mark). For example, you can write <4.3 !> 5.4!!>' to get the literal text `4.3 > 5.4!'. " Differential Revision: https://reviews.llvm.org/D32792 llvm-svn: 302652
* [IfConversion] Add missing check in IfConversion/canFallThroughToMikael Holmen2017-05-101-0/+64
| | | | | | | | | | | | | | | | | Summary: When trying to figure out if MBB could fallthrough to ToMBB (possibly by falling through a bunch of other MBBs) we didn't actually check if there was fallthrough between the last two blocks in the chain. Reviewers: kparzysz, iteratee, MatzeB Reviewed By: kparzysz, iteratee Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D32996 llvm-svn: 302650
* [SystemZ] Implement getRepRegClassFor()Jonas Paulsson2017-05-101-0/+23
| | | | | | | | | | | | This method must return a valid register class, or the list-ilp isel scheduler will crash. For MVT::Untyped nullptr was previously returned, but now ADDR128BitRegClass is returned instead. This is needed just as long as list-ilp (and probably also list-hybrid) is still there. Review: Ulrich Weigand, A Trick https://reviews.llvm.org/D32802 llvm-svn: 302649
* [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in ↵Dmitry Preobrazhensky2017-05-106-23/+23
| | | | | | | | | | | | disassembler output See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D32913 llvm-svn: 302648
* [GlobalISel][X86] Split test file. NFCIgor Breger2017-05-102-42/+44
| | | | llvm-svn: 302647
* [SystemZ] Add decimal integer instructionsUlrich Weigand2017-05-103-0/+2486
| | | | | | | This adds the set of decimal integer (BCD) instructions for assembler / disassembler use. llvm-svn: 302646
* [SystemZ] Add crypto instructionsUlrich Weigand2017-05-109-0/+296
| | | | | | | This adds the set of message-security assist instructions for assembler / disassembler use. llvm-svn: 302645
* [SystemZ] Add translate/convert instructionsUlrich Weigand2017-05-103-0/+903
| | | | | | | This adds the set of character-set translate and convert instructions for assembler / disassembler use. llvm-svn: 302644
* [SystemZ] Add missing memory/string instructionsUlrich Weigand2017-05-103-0/+452
| | | | | | | This adds a number of missing memory and string instructions for assembler / disassembler use. llvm-svn: 302643
* [SystemZ] Reformat assembler/disassembler testsUlrich Weigand2017-05-1010-6148/+6353
| | | | | | | | The assembler and disassmebler test cases started out formatted and sorted in a particular way, but this got lost over time as patches were added. Reformat them again. NFC. llvm-svn: 302642
* [DAGCombiner] Add vector support to fold (shl/srl 0, x) -> 0Simon Pilgrim2017-05-102-22/+3
| | | | llvm-svn: 302641
* Revert r301950: SpeculativeExecution: Stop using whitelist for costsChandler Carruth2017-05-102-105/+0
| | | | | | | | | | This pass doesn't correctly handle testing for when it is legal to hoist arbitrary instructions. The whitelist happens to make it safe, so before it is removed the pass's legality checks will need to be enhanced. Details have been added to the code review thread for the patch. llvm-svn: 302640
* Add a late IR expansion pass for the experimental reduction intrinsics.Amara Emerson2017-05-102-0/+211
| | | | | | | | | This pass uses a new target hook to decide whether or not to expand a particular intrinsic to the shuffevector sequence. Differential Revision: https://reviews.llvm.org/D32245 llvm-svn: 302631
* [GlobalISel][X86] G_ZEXT i1 to i32/i64 support.Igor Breger2017-05-106-1/+230
| | | | | | | | | | | | | | Summary: Support G_ZEXT i1 to i32/i64 instruction selection. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32965 llvm-svn: 302623
* [CodeGen] Don't require AA in TwoAddress at -O0.Ahmed Bougacha2017-05-101-3/+0
| | | | | | | | | | | | | This is a follow-up to r302611, which moved an -O0 computation of DT from SDAGISel to TwoAddress. Don't use it here either, and avoid computing it completely. The only use was forwarding the analysis as an optional argument to utility functions. Differential Revision: https://reviews.llvm.org/D32766 llvm-svn: 302612
* [CodeGen] Don't require AA in SDAGISel at -O0.Ahmed Bougacha2017-05-102-40/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Before r247167, the pass manager builder controlled which AA implementations were used, exporting them all in the AliasAnalysis analysis group. Now, AAResultsWrapperPass always uses BasicAA, but still uses other AA implementations if made available in the pass pipeline. But regardless, SDAGISel is required at O0, and really doesn't need to be doing fancy optimizations based on useful AA results. Don't require AA at CodeGenOpt::None, and only use it otherwise. This does have a functional impact (and one testcase is pessimized because we can't reuse a load). But I think that's desirable no matter what. Note that this alone doesn't result in less DT computations: TwoAddress was previously able to reuse the DT we computed for SDAG. That will be fixed separately. Differential Revision: https://reviews.llvm.org/D32766 llvm-svn: 302611
* [CodeGen] Compute DT/LI lazily in SafeStackLegacyPass. NFC.Ahmed Bougacha2017-05-101-3/+0
| | | | | | | | | | | | | We currently require SCEV, which requires DT/LI. Those are expensive to compute, but the pass only runs for functions that have the safestack attribute. Compute DT/LI to build SCEV lazily, only when the pass is actually going to transform the function. Differential Revision: https://reviews.llvm.org/D31302 llvm-svn: 302610
* [CodeGen] Add an -O0 backend pipeline test. NFC.Ahmed Bougacha2017-05-101-0/+71
| | | | | | | | | | | | This should hopefully makes changes to the O0 pipeline obvious; it's easy to require expensive passes, and this helps make informed decisions. Case in point: in the few weeks separating the time when I initially wrote this patch to the time when I committed, the test regressed as r302103 added another use of DT! llvm-svn: 302608
* [WebAssembly] Improve libObject support for wasm imports and exportsSam Clegg2017-05-092-16/+57
| | | | | | | | | | | | Previously we had only supported the importing and exporting of functions and globals. Also, add usefull overload of getWasmSymbol() and getNumberOfSymbols() in support of lld port. Differential Revision: https://reviews.llvm.org/D33011 llvm-svn: 302601
* [InstCombine] add tests for andn; NFCSanjay Patel2017-05-091-0/+28
| | | | llvm-svn: 302599
* [GVN] Fix a crash on encountering non-integral pointersKeno Fischer2017-05-091-0/+39
| | | | | | | | | | | | | | | | | | Summary: This fixes the immediate crash caused by introducing an incorrect inttoptr before attempting the conversion. There may still be a legality check missing somewhere earlier for non-integral pointers, but this change seems necessary in any case. Reviewers: sanjoy, dberlin Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32623 llvm-svn: 302587
* [InstCombine] update test file to use FileCheck; NFCSanjay Patel2017-05-091-14/+22
| | | | llvm-svn: 302585
* DAGCombine: Combine shuffles of splat-shufflesZvi Rackover2017-05-091-18/+16
| | | | | | | | | | | | | | Summary: Reapply r299047, but this time handle correctly splat-masks with undef elements. Reviewers: spatel, RKSimon, eli.friedman, andreadb Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31961 llvm-svn: 302583
* [AArch64] Consider widening instructions in cost calculationsMatthew Simpson2017-05-091-0/+622
| | | | | | | | | | | | | | | The AArch64 instruction set has a few "widening" instructions (e.g., uaddl, saddl, uaddw, etc.) that take one or more doubleword operands and produce quadword results. The operands are automatically sign- or zero-extended as appropriate. However, in LLVM IR, these extends are explicit. This patch updates TTI to consider these widening instructions as single operations whose cost is attached to the arithmetic instruction. It marks extends that are part of a widening operation "free" and applies a sub-target specified overhead (zero by default) to the arithmetic instructions. Differential Revision: https://reviews.llvm.org/D32706 llvm-svn: 302582
* [codeview] Check for a DIExpression offset for local variablesReid Kleckner2017-05-091-0/+41
| | | | | | | | Fixes inalloca parameters, which previously all pointed to the same offset. Extend the test to use llvm-readobj so that we can test the offset in a readable way. llvm-svn: 302578
* Make it illegal for two Functions to point to the same DISubprogramAdrian Prantl2017-05-091-5/+11
| | | | | | | | | | | | | | | | | | | As recently discussed on llvm-dev [1], this patch makes it illegal for two Functions to point to the same DISubprogram and updates FunctionCloner to also clone the debug info of a function to conform to the new requirement. To simplify the implementation it also factors out the creation of inlineAt locations from the Inliner into a general-purpose utility in DILocation. [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html <rdar://problem/31926379> Differential Revision: https://reviews.llvm.org/D32975 This reapplies r302469 with a fix for a bot failure (reparentDebugInfo now checks for the case the orig and new function are identical). llvm-svn: 302576
* [DWARF] Fix a parsing issue with type unit headers.Wolfgang Pieb2017-05-093-0/+64
| | | | | | | | Reviewers: dblaikie Differential Revision: https://reviews.llvm.org/D32987 llvm-svn: 302574
* [lanai] Add computeKnownBitsForTargetNode for Lanai.Jacques Pienaar2017-05-091-0/+48
| | | | | | | | | | | | | | Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions. Reviewers: eliben, majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29605 llvm-svn: 302568
* [WebAssembly] Fix validation of start functionSam Clegg2017-05-093-3/+20
| | | | | | | | | | The check for valid start function was inverted. Added a new test in test/Object to check this case and fixed the existing tests in for ObjectYAML. Differential Revision: https://reviews.llvm.org/D32986 llvm-svn: 302560
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