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* [AArch64] Fix test to specify triple and disable post-RA scheduling.Geoff Berry2016-05-061-1/+1
| | | | | | | This should fix bot breakage caused by r268746: [AArch64] Combine callee-save and local stack SP adjustment instructions. llvm-svn: 268752
* [SimplifyCFG] propagate branch metadata when creating select (retry r268550 ↵Sanjay Patel2016-05-061-8/+39
| | | | | | | | | | | | | | | | with possible fix) Retrying r268550 which was reverted at r268577 due a memory sanitizer failure. I have not been able to reproduce that failure, but I've taken a guess at fixing the problem in this version of the patch and will watch for another failure. Original commit message: Unlike earlier similar fixes, we need to recalculate the branch weights in this case. Differential Revision: http://reviews.llvm.org/D19674 llvm-svn: 268751
* [AArch64] Combine callee-save and local stack SP adjustment instructions.Geoff Berry2016-05-0614-87/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a function needs to allocate both callee-save stack memory and local stack memory, we currently decrement/increment the SP in two steps: first for the callee-save area, and then for the local stack area. This changes the code to allocate them both at once at the very beginning/end of the function. This has two benefits: 1) there is one fewer sub/add micro-op in the prologue/epilogue 2) the stack adjustment instructions act as a scheduling barrier, so moving them to the very beginning/end of the function increases post-RA scheduler's ability to move instructions (that only depend on argument registers) before any of the callee-save stores This change can cause an increase in instructions if the original local stack SP decrement could be folded into the first store to the stack. This occurs when the first local stack store is to stack offset 0. In this case we are trading off one more sub instruction for one fewer sub micro-op (along with benefits (2) and (3) above). Reviewers: t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18619 llvm-svn: 268746
* Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."Nikolay Haustov2016-05-061-61/+0
| | | | | | | | This reverts commit 47486d52454d60cdf6becc0b2efe533c73794380. It broke calling OpenCL kernel from another kernel. llvm-svn: 268739
* [CostModel][X86] Added costmodel tests for vector ↵Simon Pilgrim2016-05-061-0/+481
| | | | | | ctpop/ctlz/cttz/bitreverse/bswap llvm-svn: 268738
* [mips] Fix inconsistent .cprestore behaviour between direct object emission ↵Daniel Sanders2016-05-061-0/+12
| | | | | | | | | | | | | | | | | | | and assembling. Summary: Direct object emission has an initialization order problem where an InitMCObjectFile is called after MipsTargetELFStreamer determines whether PIC is enabled by default or not. There doesn't seem to be point that initializes all cases so split the responsibility between MipsTargetELFStreamer and MipsAsmPrinter. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19728 llvm-svn: 268737
* [SimplifyCFG] Prefer a simplification based on a dominating condition.Chad Rosier2016-05-061-0/+48
| | | | | | | Rather than merge two branches with a common destination. Differential Revision: http://reviews.llvm.org/D19743 llvm-svn: 268735
* [mips] Correct the ordering of HI/LO pairs in the relocation table.Daniel Sanders2016-05-061-109/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There seems to have been a misunderstanding as to the meaning of 'offset' in the rules laid down by our ABI. The previous code believed that 'offset' meant the offset within the section that the relocation is applied to. However, it should have meant the offset from the symbol used in the relocation expression. This patch adds two fields to ELFRelocationEntry and uses them to correct the order of relocations for MIPS. These fields contain: * The original symbol before shouldRelocateWithSymbol() is considered. This ensures that R_MIPS_GOT16 is able to correctly distinguish between local and external symbols, allowing us to tell whether %got() requires a matching %lo() or not (local symbols require one, external symbols don't). It also prevents confusing cases where the fuzzy matching rules cause things like %hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s. * The original offset before shouldRelocateWithSymbol() is considered. The existing Addend field is always zero when the object uses in place addends (because it's already moved it to the encoding) but MIPS needs to use the original offset to ensure that the linker correctly calculates the carry-in bit for %hi() and %got(). IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of the table to ensure that the linker rejects the table (we're unable to report such errors directly). The alternatives to this risk accidental matching against inappropriate relocations which may silently compute incorrect values due to an incorrect carry bit between the %lo() and %hi()/%got(). Reviewers: sdardis Subscribers: dsanders, sdardis, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D19718 llvm-svn: 268733
* [mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant ↵Daniel Sanders2016-05-061-2/+8
| | | | | | | | | | | | | | | | island pass. Summary: This stops it misidentifying unconditional branches as conditional branches which fixes a -verify-machineinstrs error about exiting a function via fall through. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19864 llvm-svn: 268731
* [mips][fastisel] Conditional moves do not have implicit operands.Daniel Sanders2016-05-061-2/+2
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19862 llvm-svn: 268730
* [asan] add option to set shadow mapping offsetRyan Govostes2016-05-061-0/+39
| | | | | | | | | | Allowing overriding the default ASAN shadow mapping offset with the -asan-shadow-offset option, and allow zero to be specified for both offset and scale. Patch by Aaron Carroll <aaronc@apple.com>. llvm-svn: 268724
* AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.Nikolay Haustov2016-05-061-0/+61
| | | | | | | | | | | | | | | | | Summary: Check calling convention in AMDGPUMachineFunction::isKernel This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19917 llvm-svn: 268719
* AMDGPU/SI: Add amdgpu_kernel calling convention. Part 1.Nikolay Haustov2016-05-062-1/+41
| | | | | | | | | | | | | | | | | Summary: This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. For now, also accept SPIR_KERNEL for HCC frontend. Also, add bitcode compatibility tests for missing calling conventions except AVR_BUILTIN which doesn't have parse code. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits llvm-svn: 268717
* ThinLTO: fix assertion and refactor check for hidden use from inline ASM in ↵Mehdi Amini2016-05-062-0/+36
| | | | | | | | | | | a helper function This test was crashing, and currently it breaks bootstrapping clang with debuginfo Differential Revision: http://reviews.llvm.org/D20008 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268715
* [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructionsZlatko Buljan2016-05-063-0/+54
| | | | | | Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
* [PM] port IR based PGO prof-gen pass to new pass managerXinliang David Li2016-05-0611-0/+14
| | | | llvm-svn: 268710
* [profile] Remove another unneeded field in raw profile readerXinliang David Li2016-05-066-6/+0
| | | | | | | DataValueSize is now removed. The change is consolidated with previous raw version bump. llvm-svn: 268703
* [CodeGen] Round [SU]INT_TO_FP result when promoting from f16.Ahmed Bougacha2016-05-064-5/+109
| | | | | | | | | | | | If we don't, values that aren't precisely representable in f16 could be used as-is in a promoted f32 operation, which would produce incorrect results. AArch64 had the correct behavior; add a focused test. Fixes http://llvm.org/PR26871 llvm-svn: 268700
* [PM] port Branch Frequency Analaysis pass to new PMXinliang David Li2016-05-0510-0/+10
| | | | llvm-svn: 268687
* [PM] Port Interprocedural SCCP to the new pass manager.Davide Italiano2016-05-051-0/+1
| | | | llvm-svn: 268684
* Revert http://reviews.llvm.org/D19926 as it breaks tests.Dehao Chen2016-05-052-6/+19
| | | | llvm-svn: 268681
* [WebAssembly] Don't emit epilogue code in the middle of stackified code.Dan Gohman2016-05-051-0/+12
| | | | llvm-svn: 268679
* Simplify CFG before assigning discriminator.Dehao Chen2016-05-052-19/+6
| | | | | | | | | | | | Summary: We need to clean up CFG before assigning discriminator to minimize the impact of optimization on debug info. Reviewers: davidxl, dblaikie, dnovillo Subscribers: dnovillo, danielcdh, llvm-commits Differential Revision: http://reviews.llvm.org/D19926 llvm-svn: 268675
* [MSan] [MIPS64] Fix vararg helper for >1 fixed argument.Marcin Koscielnicki2016-05-052-0/+24
| | | | | | | | This fixes http://llvm.org/PR27646 on Mips64. Differential Revision: http://reviews.llvm.org/D19989 llvm-svn: 268673
* AMDGPU: Run r600 tests lastMatt Arsenault2016-05-0525-48/+47
| | | | llvm-svn: 268672
* ARM: don't attempt to merge litpools referencing different PC-anchors.Tim Northover2016-05-051-0/+46
| | | | | | | | | | | | | | | | | | | | | | Given something like: ldr r0, .LCPI0_0 (== pc-rel var) add r0, pc ldr r1, .LCPI0_1 (== pc-rel var) add r1, pc we cannot combine the 2 ldr instructions and litpools because they get added to a different pc to form the correct address. I think the original logic came from a time when we fused the LDRpci/PICADD instructions into one pseudo-instruction so the PC was always immediately at-hand. That's no longer the case. Should fix general-dynamic TLS access on Linux, and quite possibly other -fPIC code that relies on litpools (e.g. v6m and -Oz compilations) though trivial tweaks of the .ll test didn't provoke anything. llvm-svn: 268662
* [Hexagon] Add aliases for vector loads/stores with no explicit offsetKrzysztof Parzyszek2016-05-051-0/+61
| | | | | | The mem(r0) instructions are treated as mem(r0+#0). llvm-svn: 268661
* Revert "[ThinLTO] Emit individual index files for distributed backends"Vitaly Buka2016-05-053-86/+1
| | | | | | | | | MemorySanitizer: use-of-uninitialized-value in lib/Bitcode/Writer/BitcodeWriter.cpp:364:70 http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/12544/steps/check-llvm%20msan/logs/stdio This reverts commit 0c4a898ea550699d1b2f4fe3767251c8f9a48d52. llvm-svn: 268660
* Clean up the specific error message for a malformed Mach-O files with bad ↵Kevin Enderby2016-05-052-4/+8
| | | | | | | | | | | | | | | | | | | | | segment load commands. The existing test case in test/Object/macho-invalid.test for macho-invalid-too-small-segment-load-command has a cmdsize of 55, while being too small also it is not a multiple of 4. So when that check is added this test case will produce a different error. So I constructed a new test case that will trigger the intended error. I also changed the error message to be consistent with the other malformed Mach-O file error messages which prints the load command index. I also removed both object_error::macho_load_segment_too_small and object_error::macho_load_segment_too_many_sections from Object/Error.h as they are not needed and can just use object_error::parse_failed and let the error message string distinguish the specific error. llvm-svn: 268652
* AMDGPU: Uniform branch conditions can originate with intrinsicsNicolai Haehnle2016-05-051-0/+27
| | | | | | | | | | | | | | | | | Summary: Discovered by Dave Airlie, fixes an assertion in Khronos OpenGL CTS GL43-CTS.shader_storage_buffer_object.advanced-matrix. In this particular case, the buffer load intrinsic fed into a uniform conditional branch, and led the brcond lowering down the wrong path. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19931 llvm-svn: 268650
* AMDGPU/SI: Add support for AMD code object version 2.Tom Stellard2016-05-057-207/+41
| | | | | | | | | | | | | | Summary: Version 2 is now the default. If you want to emit version 1, use the amdgcn--amdhsa-amdcov1 triple. Reviewers: arsenm, kzhuravl Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19283 llvm-svn: 268647
* [ValueTracking] Improve isImpliedCondition for matching LHS and Imm RHSs.Chad Rosier2016-05-054-8/+151
| | | | llvm-svn: 268636
* [LV] Identify more induction PHIs by coercing expressions to AddRecExprsSilviu Baranga2016-05-051-0/+75
| | | | | | | | | | | | | | | | | | Summary: Some PHIs can have expressions that are not AddRecExprs due to the presence of sext/zext instructions. In order to prevent the Loop Vectorizer from bailing out when encountering these PHIs, we now coerce the SCEV expressions to AddRecExprs using SCEV predicates (when possible). We only do this when the alternative would be to not vectorize. Reviewers: mzolotukhin, anemet Subscribers: mssimpso, sanjoy, mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D17153 llvm-svn: 268633
* Remove bit-rotten CppBackend.James Y Knight2016-05-058-163/+0
| | | | | | | | | | | | | | | | | This backend was supposed to generate C++ code which will re-construct the LLVM IR passed as input. This seems to me to have very marginal usefulness in the first place. However, the code has never been updated to use IRBuilder, which makes its current value negative -- people who look at the output may be steered to use the *wrong* C++ APIs to construct IR. Furthermore, it's generated code that doesn't compile since at least 2013. Differential Revision: http://reviews.llvm.org/D19942 llvm-svn: 268631
* Fix Mips Parser error reportingNirav Dave2016-05-051-1/+8
| | | | | | | | | | | | | [mips] On error, ParseDirective should always return false to signify that the directive was understood. Reviewers: dsanders, vkalintiris, sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19929 llvm-svn: 268630
* Fix Windows bot failures from r268627Teresa Johnson2016-05-051-3/+3
| | | | | | | | | | Remove "/" path separator from expected pattern which should fix a couple of Windows bots that have failed: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/4816 http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/2610 llvm-svn: 268629
* [ThinLTO] Emit individual index files for distributed backendsTeresa Johnson2016-05-053-1/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When launching ThinLTO backends in a distributed build (currently supported in gold via the thinlto-index-only plugin option), emit an individual index file for each backend process as described here: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098272.html The individual index file encodes the summary and module information required for implementing the importing/exporting decisions made for a given module in the thin link step. This is in place of the current mechanism that uses the combined index to make importing decisions in each back end independently. It is an enabler for doing global summary based optimizations in the thin link step (which will be recorded in the individual index files), and reduces the size of the index that must be sent to each backend process, and the amount of work to scan it in the backends. Rather than create entirely new ModuleSummaryIndex structures (and all the included unique_ptrs) for each backend index file, a map is created to record all of the GUID and summary pointers needed for a particular index file. The IndexBitcodeWriter walks this map instead of the full index (hiding the details of managing the appropriate summary iteration in a new iterator subclass). This is more efficient than walking the entire combined index and filtering out just the needed summaries during each backend bitcode index write. Depends on D19481. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19556 llvm-svn: 268627
* [X86] Extend some Linux special cases to cover kFreeBSD.Marcin Koscielnicki2016-05-052-0/+7
| | | | | | | | | | | | Both Linux and kFreeBSD use glibc, so follow similiar code paths. Add isTargetGlibc to check for this, and use it instead of isTargetLinux in a few places. Fixes PR22248 for kFreeBSD. Differential Revision: http://reviews.llvm.org/D19104 llvm-svn: 268624
* [Coverage] Combine counts of expansion regions if there are no code regions ↵Igor Kudrin2016-05-053-0/+34
| | | | | | | | for the same area. Differential Revision: http://reviews.llvm.org/D18831 llvm-svn: 268620
* [X86] Use the right type when folding xor (truncate (shift)) -> setccDavid Majnemer2016-05-051-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The result type of setcc is dependent on whether or not AVX512 is present. We had an X86-specific DAG-combine which assumed that the result type should be i8 when it could be i1. This meant that we would generate illegal setccs which LowerSETCC did not like. Instead, use an appropriate type and zero extend to i8. Also, there were some scenarios where the fold should have fired but didn't because we were overly cautious about the types. This meant that we generated: shrl $31, %edi andl $1, %edi kmovw %edi, %k0 kxnorw %k0, %k0, %k1 kshiftrw $15, %k1, %k1 kxorw %k1, %k0, %k0 kmovw %k0, %eax instead of: testl %edi, %edi setns %al This fixes PR27638. llvm-svn: 268609
* LTOCodeGenerator: add linkonce(_odr) to "llvm.compiler.used" when present in ↵Mehdi Amini2016-05-051-4/+11
| | | | | | | | | | | | | | | "MustPreserve" set If the linker requested to preserve a linkonce function, we should honor this even if we drop all uses. We explicitely avoid turning them into weak_odr (unlike the first version of this patch in r267644), because the codegen can be different on Darwin: because of `llvm::canBeOmittedFromSymbolTable()` we may emit the symbol as weak_def_can_be_hidden instead of weak_definition. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268607
* Revert "LTOCodeGenerator: turns linkonce(_odr) into weak_(odr) when present ↵Mehdi Amini2016-05-051-5/+3
| | | | | | | | | | | | "MustPreserve" set" This reverts commit r267644. Turning linkonce_odr into weak_odr is a sementic change on Darwin: because of `llvm::canBeOmittedFromSymbolTable()` we may emit the symbol as weak_def_can_be_hidden instead of weak_definition. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268606
* [Profile] Raw profile header clean upXinliang David Li2016-05-056-12/+6
| | | | | | Remove dead ValueDataBegin field in raw header. llvm-svn: 268602
* [PM] Port Branch Probability Analysis pass to the new pass manager.Xinliang David Li2016-05-056-1/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D19839 llvm-svn: 268601
* [PM] Port EliminateAvailableExternally pass to the new pass manager.Davide Italiano2016-05-051-1/+1
| | | | llvm-svn: 268599
* Revert "[asan] add option to set shadow mapping offset"Ryan Govostes2016-05-051-39/+0
| | | | | | This reverts commit ba89768f97b1d4326acb5e33c14eb23a05c7bea7. llvm-svn: 268588
* [asan] add option to set shadow mapping offsetRyan Govostes2016-05-051-0/+39
| | | | | | | | Allowing overriding the default ASAN shadow mapping offset with the -asan-shadow-offset option, and allow zero to be specified for both offset and scale. llvm-svn: 268586
* [PM] Port ConstantMerge to the new pass manager.Davide Italiano2016-05-051-1/+1
| | | | llvm-svn: 268582
* [SystemZ] Implement backchain attribute (recommit with fix).Marcin Koscielnicki2016-05-051-0/+84
| | | | | | | | | | | | | This introduces a SystemZ-specific "backchain" attribute on function, which enables writing the frame backchain link as specified by the ABI. This will be used to implement -mbackchain option in clang. Differential Revision: http://reviews.llvm.org/D19889 Fixed in this version: added RegState::Define and RegState::Kill on R1D in prologue. llvm-svn: 268581
* [LoopDataPrefetch] Add optimization remarkAdam Nemet2016-05-051-0/+78
| | | | | | | With -Rpass=loop-data-prefetch, show the memory access that got prefetched. llvm-svn: 268578
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