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* Teach machine block placement to cope with unnatural loops. These don'tChandler Carruth2011-11-141-0/+37
| | | | | | | | | | | | | | | | | | get loop info structures associated with them, and so we need some way to make forward progress selecting and placing basic blocks. The technique used here is pretty brutal -- it just scans the list of blocks looking for the first unplaced candidate. It keeps placing blocks like this until the CFG becomes tractable. The cost is somewhat unfortunate, it requires allocating a vector of all basic block pointers eagerly. I have some ideas about how to simplify and optimize this, but I'm trying to get the logic correct first. Thanks to Benjamin Kramer for the reduced test case out of GCC. Sadly there are other bugs that GCC is tickling that I'm reducing and working on now. llvm-svn: 144516
* Rewrite #3 of machine block placement. This is based somewhat on theChandler Carruth2011-11-131-1/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | second algorithm, but only loosely. It is more heavily based on the last discussion I had with Andy. It continues to walk from the inner-most loop outward, but there is a key difference. With this algorithm we ensure that as we visit each loop, the entire loop is merged into a single chain. At the end, the entire function is treated as a "loop", and merged into a single chain. This chain forms the desired sequence of blocks within the function. Switching to a single algorithm removes my biggest problem with the previous approaches -- they had different behavior depending on which system triggered the layout. Now there is exactly one algorithm and one basis for the decision making. The other key difference is how the chain is formed. This is based heavily on the idea Andy mentioned of keeping a worklist of blocks that are viable layout successors based on the CFG. Having this set allows us to consistently select the best layout successor for each block. It is expensive though. The code here remains very rough. There is a lot that needs to be done to clean up the code, and to make the runtime cost of this pass much lower. Very much WIP, but this was a giant chunk of code and I'd rather folks see it sooner than later. Everything remains behind a flag of course. I've added a couple of tests to exercise the issues that this iteration was motivated by: loop structure preservation. I've also fixed one test that was exhibiting the broken behavior of the previous version. llvm-svn: 144495
* The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier2011-11-131-3/+4
| | | | | | mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. llvm-svn: 144494
* Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier2011-11-131-1/+0
| | | | | | failures. llvm-svn: 144492
* Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier2011-11-131-0/+80
| | | | | | | | | | | | | SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 llvm-svn: 144488
* Remove the -color-ss-with-regs option.Jakob Stoklund Olesen2011-11-131-55/+0
| | | | | | | | | It was off by default. The new register allocators don't have the problems that made it necessary to reallocate registers during stack slot coloring. llvm-svn: 144481
* Delete the 'standard' spiller with used the old spilling framework.Jakob Stoklund Olesen2011-11-121-1/+1
| | | | | | The current register allocators all use the inline spiller. llvm-svn: 144477
* Remove histogram tests.Jakob Stoklund Olesen2011-11-122-56/+0
| | | | | | Counting the number of occurences of each opcode is not a useful test. llvm-svn: 144474
* RAGreedy is better about hinting now.Jakob Stoklund Olesen2011-11-121-1/+1
| | | | | | Or maybe we are just getting lucky. llvm-svn: 144473
* Linear scan is going away.Jakob Stoklund Olesen2011-11-124-8/+6
| | | | llvm-svn: 144472
* XFAIL test that depends on linear scan to remove dead code.Jakob Stoklund Olesen2011-11-121-1/+3
| | | | | | | Filed PR11364 to track the problem. Should the register allocator eliminate dead code? llvm-svn: 144471
* Remove obsolete test.Jakob Stoklund Olesen2011-11-121-51/+0
| | | | | | | This test was committed with a bugfix to RemoveCopyByCommutingDef, but that optimization is no longer triggered by this test. llvm-svn: 144470
* Remove obsolete test.Jakob Stoklund Olesen2011-11-121-167/+0
| | | | | | | This test is for a very specific LocalRewriter bug. LocalRewriter is going away. llvm-svn: 144469
* Remove obsolete test.Jakob Stoklund Olesen2011-11-121-54/+0
| | | | | | | I don't think this test does what is was supposed to do, and LocalRewriter is going away anyway. llvm-svn: 144463
* Eliminate more linear scan tests.Jakob Stoklund Olesen2011-11-123-6/+6
| | | | llvm-svn: 144462
* Switch a couple -O0 tests to RABasic.Jakob Stoklund Olesen2011-11-123-5/+7
| | | | llvm-svn: 144461
* Switch a few tests off linearscan.Jakob Stoklund Olesen2011-11-123-4/+5
| | | | llvm-svn: 144460
* Delete old test of a VirtRegRewriter feature.Jakob Stoklund Olesen2011-11-121-49/+0
| | | | | | | | This test doesn't expose the issue with RAGreedy. I filed PR11363 to track the missing InlineSpiller feature. llvm-svn: 144459
* Remove old test that doesn't make sense.Jakob Stoklund Olesen2011-11-121-13/+0
| | | | | | | The test is checking that the output doesn't contains any 'mov ' strings. It does contain movl, though. llvm-svn: 144458
* Add more AVX2 shift lowering support. Move AVX2 variable shift to use ↵Craig Topper2011-11-121-0/+39
| | | | | | patterns instead of custom lowering code. llvm-svn: 144457
* Don't try to loop on iterators that are potentially invalidated inside the ↵Nick Lewycky2011-11-121-0/+42
| | | | | | loop. Fixes PR11361! llvm-svn: 144454
* Make sure scalarrepl picks the correct alloca when it rewrites a bitcast. ↵Eli Friedman2011-11-121-0/+26
| | | | | | Fixes PR11353. llvm-svn: 144442
* The dwarf standard says that the only differences between a out-of-lineRafael Espindola2011-11-121-0/+97
| | | | | | | | | | | | | | instance and a concrete inlined instance are the use of DW_TAG_subprogram instead of DW_TAG_inlined_subroutine and the who owns the tree. We were also omitting DW_AT_inline from the abstract roots. To fix this, make sure we mark abstract instance roots with DW_AT_inline even when we have only out-of-line instances referring to them with DW_AT_abstract_origin. FileCheck is not a very good tool for tests like this, maybe we should add a -verify mode to llvm-dwarfdump. llvm-svn: 144441
* Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman2011-11-121-0/+22
| | | | | | runs. Fixes PR11029. llvm-svn: 144438
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+10
| | | | llvm-svn: 144427
* Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier2011-11-111-0/+78
| | | | llvm-svn: 144426
* Loosen test by using REs. Approved by Devang.Chad Rosier2011-11-111-1/+1
| | | | llvm-svn: 144425
* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-111-0/+15
| | | | | | Fixes PR8113. llvm-svn: 144409
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-0/+2
| | | | | | rdar://9672822 llvm-svn: 144407
* Move X86 specific test in X86 directory.Devang Patel2011-11-111-0/+0
| | | | llvm-svn: 144395
* Move X86 specific test in X86 directory.Devang Patel2011-11-111-0/+0
| | | | llvm-svn: 144394
* allow non-device function calls in PTX when natively handling device-side printfDan Bailey2011-11-111-0/+25
| | | | llvm-svn: 144388
* Add lowering for AVX2 shift instructions.Craig Topper2011-11-112-73/+210
| | | | llvm-svn: 144380
* Add support for using immediates with select instructions.Chad Rosier2011-11-111-0/+99
| | | | | | rdar://10412592 llvm-svn: 144376
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-111-0/+9
| | | | llvm-svn: 144361
* Get rid of an optimization in SCCP which appears to have many issues. ↵Eli Friedman2011-11-111-20/+0
| | | | | | | | | | Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which lead to it trying to re-mark a value marked as a constant with a different value. It also appears to trigger very rarely. Fixes PR11357. llvm-svn: 144352
* Add support for using MVN to materialize negative constants.Chad Rosier2011-11-112-6/+113
| | | | | | rdar://10412592 llvm-svn: 144348
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-101-0/+15
| | | | | | rdar://10130228. llvm-svn: 144331
* Check in getOrCreateSubprogramDIE if a declaration exists and if so outputRafael Espindola2011-11-101-0/+43
| | | | | | | | it first. This is a more general fix to pr11300. llvm-svn: 144324
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-101-0/+2
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
* When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier2011-11-101-0/+138
| | | | | | | For correctness, disable this for now. rdar://10418009 llvm-svn: 144316
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-102-6/+33
| | | | | | More of rdar://9704684 llvm-svn: 144301
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-101-1/+8
| | | | | | Start of rdar://9704684 llvm-svn: 144293
* test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd ↵NAKAMURA Takumi2011-11-101-1/+1
| | | | | | | | bots to specify explicit -mtriple=x86_64-darwin. I guess it expects -relocation-model=pic. llvm-svn: 144290
* Use a bigger hammer to fix PR11314 by disabling the "forcing two-addressEvan Cheng2011-11-1011-20/+31
| | | | | | | | | | | | | | | | instruction lower optimization" in the pre-RA scheduler. The optimization, rather the hack, was done before MI use-list was available. Now we should be able to implement it in a better way, perhaps in the two-address pass until a MI scheduler is available. Now that the scheduler has to backtrack to handle call sequences. Adding artificial scheduling constraints is just not safe. Furthermore, the hack is not taking all the other scheduling decisions into consideration so it's just as likely to pessimize code. So I view disabling this optimization goodness regardless of PR11314. llvm-svn: 144267
* For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier2011-11-101-0/+17
| | | | | | | determine if the value is negative and flip the sign accordingly. rdar://10422026 llvm-svn: 144258
* Strip old implicit operands after foldMemoryOperand.Jakob Stoklund Olesen2011-11-101-0/+105
| | | | | | | | | | | | The TII.foldMemoryOperand hook preserves implicit operands from the original instruction. This is not what we want when those implicit operands refer to the register being spilled. Implicit operands referring to other registers are preserved. This fixes PR11347. llvm-svn: 144247
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-091-0/+2
| | | | | | rdar://10422955 llvm-svn: 144242
* Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman2011-11-091-0/+37
| | | | llvm-svn: 144241
* DeadStoreElimination can now trim the size of a store if the end of the ↵Pete Cooper2011-11-091-0/+78
| | | | | | | | | | | store is dead. Currently checks alignment and killing stores on a power of 2 boundary as this is likely to trim the size of the earlier store without breaking large vector stores into scalar ones. Fixes <rdar://problem/10140300> llvm-svn: 144239
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