summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* fix an encoding mismatch where "sal %eax, 1" was not using the short encodingChris Lattner2010-10-301-0/+5
| | | | | | for shl. Caught by inspection. llvm-svn: 117820
* add a test for the ud2a alias.Chris Lattner2010-10-301-0/+4
| | | | llvm-svn: 117803
* If a function does a volatile load from a global constant, do notDuncan Sands2010-10-301-0/+10
| | | | | | | | | consider it to be readonly. In fact, don't even consider it to be readonly if it does a volatile load from an AllocaInst either (it is debatable as to whether readonly would be correct or not in this case; play safe for the moment). This fixes PR8279. llvm-svn: 117783
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-302-14/+28
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-292-434/+160
| | | | | | conditional. Check for those instructions explicitly. llvm-svn: 117747
* Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng2010-10-291-1/+7
| | | | | | defs. rdar://8610857. llvm-svn: 117745
* Be more strict on when we produce an undefined reference. In gas a file withRafael Espindola2010-10-293-1/+4
| | | | | | | | | | | | | | | | | | | | | | | just .type foo,@object will produce an undefined reference to foo. On the other hand, a file with just .weakref bar, foo will not. It is somewhat hard to support both in MC since both statements should create the symbols. It should be possible if we really need to by adding to the flags, but hopefully that is not necessary. With this patch we do not produce a undefined reference in any of those cases. The assembly file needs an actual use for the undefined reference to be present. This is in preparation for a patch implementing .weakref. llvm-svn: 117735
* Change instcombine's getShuffleMask to represent undef with negative values.Bob Wilson2010-10-291-0/+13
| | | | | | | | This code had previously used 2*N, where N is the mask length, to represent undef. That is not safe because the shufflevector operands may have more than N elements -- they don't have to match the result type. llvm-svn: 117721
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-16/+0
| | | | llvm-svn: 117720
* Make instcombine a little more aggressive in combining vector shuffles.Bob Wilson2010-10-291-0/+10
| | | | | | | | Allow splats even if they don't match either of the original shuffles, possibly due to undef entries in the shuffles masks. Radar 8597790. Also fix some 80-column violations. llvm-svn: 117719
* Update testcase since we're no longer doing the constant forwarding inline ↵Owen Anderson2010-10-291-2/+1
| | | | | | with correlated value propagation. llvm-svn: 117712
* Convert this test to .s form.Owen Anderson2010-10-292-625/+150
| | | | llvm-svn: 117708
* Convert this test to .s form.Owen Anderson2010-10-292-85/+26
| | | | llvm-svn: 117704
* Convert this test to .s form.Owen Anderson2010-10-292-121/+26
| | | | llvm-svn: 117699
* Convert this test to .s form.Owen Anderson2010-10-292-427/+87
| | | | llvm-svn: 117696
* Covert this test to .s form.Owen Anderson2010-10-292-107/+30
| | | | llvm-svn: 117694
* Convert this test to .s form.Owen Anderson2010-10-292-278/+56
| | | | llvm-svn: 117693
* Convert this test to .s form.Owen Anderson2010-10-292-381/+67
| | | | llvm-svn: 117690
* Convert this test to .s form.Owen Anderson2010-10-292-431/+117
| | | | llvm-svn: 117689
* Convert this test to .s form.Owen Anderson2010-10-292-295/+58
| | | | llvm-svn: 117686
* Convert this test to .s form.Owen Anderson2010-10-292-115/+27
| | | | llvm-svn: 117685
* Covert this test to .s form.Owen Anderson2010-10-292-122/+34
| | | | llvm-svn: 117684
* Convert this test to .s form.Owen Anderson2010-10-292-477/+104
| | | | llvm-svn: 117683
* Convert this test to .s form.Owen Anderson2010-10-292-143/+36
| | | | llvm-svn: 117682
* Convert this file to less fragile .s form.Owen Anderson2010-10-292-118/+32
| | | | llvm-svn: 117681
* Replace this test with the less fragile .s version. Still XFAIL'd, since ↵Owen Anderson2010-10-292-412/+84
| | | | | | the ASM parser doesn't parse vabal yet. llvm-svn: 117679
* Covert this test to a .s file to reduce fragility.Owen Anderson2010-10-292-117/+31
| | | | llvm-svn: 117676
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-292-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* test/Scripts/macho-dump: Make hack for Python-2.4. [PR7995]NAKAMURA Takumi2010-10-291-1/+4
| | | | | | | | | With Python-2.4, Reader::read64 always returns (unexpected) long integer. FileCheck detects failure on test/MC/MachO among '0' and '0L'. CentOS5(aka RHEL5 clone) provides python-2.4. llvm-svn: 117637
* Teach memdep to use pointsToConstantMemory to determine that loadsDan Gohman2010-10-291-0/+23
| | | | | | from constant memory don't alias any stores. llvm-svn: 117636
* Convert this test to a .s file, so that it's not sensitive to codegen changes.Owen Anderson2010-10-293-658/+138
| | | | llvm-svn: 117633
* Add a basic testcase for TBAA-aware DSE.Dan Gohman2010-10-291-0/+43
| | | | llvm-svn: 117632
* add simple support for addrmode5 operands, allowingChris Lattner2010-10-291-0/+4
| | | | | | | vldr.64 to work. I have no idea if this is fully right, but it is in the right direction. llvm-svn: 117626
* The ARM jit cannot handle these tests as of 2010-10-27.Andrew Trick2010-10-292-0/+2
| | | | | | (A PR will be linked to this rev.) llvm-svn: 117620
* Improvements to .section parsing:Rafael Espindola2010-10-281-0/+5
| | | | | | | | | | * If we have a M or a G, reject sections without the type * Only parse the flag specific arguments if we have M or G * Parse the corresponding arguments for M and G We ignore the G arguments and flag for now. llvm-svn: 117608
* most simple arm instructions match correctly now,Chris Lattner2010-10-281-0/+5
| | | | | | it looks like we're not handling [] operands though llvm-svn: 117607
* fix the asmmatcher generator to handle targets with no RegisterPrefixChris Lattner2010-10-281-1/+6
| | | | | | | (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. llvm-svn: 117606
* Add support for the .string directive.Rafael Espindola2010-10-281-0/+7
| | | | llvm-svn: 117592
* Defined weak symbols should have non-zero value.Rafael Espindola2010-10-281-2/+2
| | | | llvm-svn: 117585
* Fix relocations with renamed symbols.Rafael Espindola2010-10-281-0/+46
| | | | llvm-svn: 117575
* Aliases defined with .symver should copy the binding of the symbols they alias.Rafael Espindola2010-10-281-3/+26
| | | | | | | Move the existing patching for undefined symbols so that all the patching is done in the same function. llvm-svn: 117570
* Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson2010-10-281-0/+16
| | | | | | Also do some minor refactoring to reduce indentation. llvm-svn: 117558
* Implement .equ directive as a synonym to .set.Roman Divacky2010-10-281-0/+5
| | | | llvm-svn: 117553
* Testcase for PR8494 (invalid bitcode crashing the bitcode reader).Duncan Sands2010-10-282-0/+2
| | | | llvm-svn: 117552
* Implement R_X86_64_DTPOFF32.Rafael Espindola2010-10-281-0/+7
| | | | llvm-svn: 117548
* Implement TLSLD.Rafael Espindola2010-10-281-0/+7
| | | | llvm-svn: 117547
* Implement DTPOFF.Rafael Espindola2010-10-281-0/+9
| | | | llvm-svn: 117546
* Implement TLSLDM.Rafael Espindola2010-10-281-0/+7
| | | | llvm-svn: 117544
* Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind.Rafael Espindola2010-10-281-0/+9
| | | | llvm-svn: 117543
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-287-8/+8
| | | | llvm-svn: 117531
OpenPOWER on IntegriCloud