summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* [MachineOutliner] XFAIL machine-outliner-noredzone.llJessica Paquette2018-04-201-2/+3
| | | | | | | | | | The verifier began complaining about an undefined physical register in this test. XFAILing for the purposes of getting a bot up while I look into it. Failure: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/11385/ llvm-svn: 330493
* [ObjCARC] Account for funclet token in storeStrong transformShoaib Meenai2018-04-201-0/+37
| | | | | | | | | | | | | | When creating a call to storeStrong in ObjCARCContract, ensure the call gets the correct funclet token, otherwise WinEHPrepare will turn the call (and all subsequent instructions) into unreachable. We already have logic to do this for the ARC autorelease elision marker; factor that out into a common function that's used for both. These are the only two places in this transform that create call instructions. Differential Revision: https://reviews.llvm.org/D45857 llvm-svn: 330487
* [llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge testsSimon Pilgrim2018-04-209-0/+2733
| | | | llvm-svn: 330486
* [X86] Add WriteFSign/WriteFLogic scheduler classesSimon Pilgrim2018-04-205-851/+851
| | | | | | | | | | | | | | Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes. This unearthed a couple of things that are also handled in this patch: (1) We were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic (2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015. (3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops. Differential Revision: https://reviews.llvm.org/D45629 llvm-svn: 330480
* [llvm-objcopy] Fix sh_linkAlexander Shaposhnikov2018-04-202-1/+49
| | | | | | | | | | | | This diff fixes sh_link for various types of sections (i.e. for SHT_ARM_EXIDX, SHT_HASH). In particular, this change enables us to use llvm-objcopy with clang -gsplit-dwarf for the target android-arm. Test plan: make check-all Differential revision: https://reviews.llvm.org/D45851 llvm-svn: 330478
* [HWASan] Introduce non-zero based and dynamic shadow memory (LLVM).Alex Shlyapnikov2018-04-202-15/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Support the dynamic shadow memory offset (the default case for user space now) and static non-zero shadow memory offset (-hwasan-mapping-offset option). Keeping the the latter case around for functionality and performance comparison tests (and mostly for -hwasan-mapping-offset=0 case). The implementation is stripped down ASan one, picking only the relevant parts in the following assumptions: shadow scale is fixed, the shadow memory is dynamic, it is accessed via ifunc global, shadow memory address rematerialization is suppressed. Keep zero-based shadow memory for kernel (-hwasan-kernel option) and calls instreumented case (-hwasan-instrument-with-calls option), which essentially means that the generated code is not changed in these cases. Reviewers: eugenis Subscribers: srhines, llvm-commits Differential Revision: https://reviews.llvm.org/D45840 llvm-svn: 330475
* [PartialInlining] Fix Crash from holding a reference to a destructed ORE.Sean Fertile2018-04-201-0/+170
| | | | | | | | | | | | | The callback used to create an ORE for the legacy PI pass caches the allocated object in a unique_ptr in the runOnModule function, and returns a reference to that object. Under certian circumstances we can end up holding onto that reference after the OREs destruction. Rather then allowing the new and legacy passes to create ORE object in diffrent ways, create the ORE at the point of use. Differential Revision: https://reviews.llvm.org/D43219 llvm-svn: 330473
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-202-0/+76
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Skip fixed-stack indexes in HexagonConstExtendersKrzysztof Parzyszek2018-04-201-0/+51
| | | | | | | Fixed slots have negative values, and TRI::stackSlot2Index and TRI::index2StackSlot do not handle negative numbers. llvm-svn: 330468
* [X86] WaitPKG instructionsGabor Buella2018-04-207-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three new instructions: umonitor - Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a writeback memory caching type. umwait - A hint that allows the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. tpause - Directs the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX. Also modifying the description of the mfence instruction, as the rep prefix (0xF3) was allowed before, which would conflict with umonitor during disassembly. Before: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text mfence After: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text umonitor %rax Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45253 llvm-svn: 330462
* [MachineOutliner] Change B instruction for tail calls to TCRETURNdiJessica Paquette2018-04-201-2/+2
| | | | | | | | | | First off, this is more correct than having the B. Second off, this was making a bot upset. This fixes that. Update the test to include -verify-machineinstrs as well to prevent stuff like this slipping by non debug/assert builds in the future. llvm-svn: 330459
* [x86] auto-generate checks; NFCSanjay Patel2018-04-201-213/+411
| | | | | | | There's a proposal to change/add to this file in D45653, so we should know exactly what those differences would be. llvm-svn: 330445
* [NewGVN] Split OpPHI detection and creation.Florian Hahn2018-04-201-0/+51
| | | | | | | | | | | | | It also adds a check making sure PHIs for operands are all in the same block. Patch by Daniel Berlin <dberlin@dberlin.org> Reviewers: dberlin, davide Differential Revision: https://reviews.llvm.org/D43865 llvm-svn: 330444
* [DebugInfo] Use WithColor for more debug line warningsAndrew Ng2018-04-202-2/+2
| | | | | | | | | | Updated two more debug line related warnings to use WithColor. This was necessary to ensure consistent output order of the warnings on Windows for debug line tests. Differential Revision: https://reviews.llvm.org/D45871 llvm-svn: 330440
* [CostModel][X86] Add vector element insert/extract cost testsSimon Pilgrim2018-04-202-0/+718
| | | | llvm-svn: 330439
* Fix test by allowing it to accept an upper or lower case letter as the first ↵Douglas Yung2018-04-201-1/+1
| | | | | | | | character. Windows for some reason uses a lower case letter, while linux uses upper case. llvm-svn: 330438
* [DAGCombine] (float)((int) f) --> ftrunc (PR36617)Sanjay Patel2018-04-208-330/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed at rL328921 and reverted at rL329920 to investigate failures in Chrome. This time I've added to the ReleaseNotes to warn users of the potential of exposing UB and let me repeat that here for more exposure: Optimization of floating-point casts is improved. This may cause surprising results for code that is relying on undefined behavior. Code sanitizers can be used to detect affected patterns such as this: int main() { float x = 4294967296.0f; x = (float)((int)x); printf("junk in the ftrunc: %f\n", x); return 0; } $ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of representable values of type 'int' junk in the ftrunc: 0.000000 Original commit message: fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC, so replace a pair of casts with the equivalent node. We don't have to account for special cases (NaN, INF) because out-of-range casts are undefined. Differential Revision: https://reviews.llvm.org/D44909 llvm-svn: 330437
* [CostModel][X86] Add srem/urem constant cost testsSimon Pilgrim2018-04-201-0/+248
| | | | llvm-svn: 330436
* [CostModel][X86] Add SLM/GLM/BtVer2 compare + division/remainder cost testsSimon Pilgrim2018-04-203-0/+194
| | | | llvm-svn: 330435
* Fix typo in a test.Michael Zolotukhin2018-04-201-1/+1
| | | | llvm-svn: 330434
* [CostModel][X86] Split off BtVer2 cost checksSimon Pilgrim2018-04-2015-101/+1454
| | | | llvm-svn: 330433
* [CostModel][X86] Add GoldmontPlus cost testsSimon Pilgrim2018-04-201-0/+1
| | | | | | Just reuses goldmont costs atm llvm-svn: 330432
* Revert "Revert r330403 and r330413."Michael Zolotukhin2018-04-201-0/+54
| | | | | | | | | | | Reapply the patches with a fix. Thanks Ilya and Hans for the reproducer! This reverts commit r330416. The issue was that removing predecessors invalidated uses that we stored for rewrite. The fix is to finish manipulating with CFG before we select uses for rewrite. llvm-svn: 330431
* [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load ↵Sander de Smalen2018-04-2014-0/+343
| | | | | | | | | | | | | | | | | | | instructions. This is patch [4/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45690 llvm-svn: 330423
* Require asserts for stats-file-option tests.Florian Hahn2018-04-202-0/+4
| | | | llvm-svn: 330417
* Revert r330403 and r330413.Ilya Biryukov2018-04-201-28/+0
| | | | | | | | | | | | | | | | Revert r330413: "[SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites." Revert r330403 "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time." r330403 commit seems to crash clang during our integrate while doing PGO build with the following stacktrace: #2 llvm::SSAUpdaterBulk::RewriteAllUses(llvm::DominatorTree*, llvm::SmallVectorImpl<llvm::PHINode*>*) #3 llvm::JumpThreadingPass::ThreadEdge(llvm::BasicBlock*, llvm::SmallVectorImpl<llvm::BasicBlock*> const&, llvm::BasicBlock*) #4 llvm::JumpThreadingPass::ProcessThreadableEdges(llvm::Value*, llvm::BasicBlock*, llvm::jumpthreading::ConstantPreference, llvm::Instruction*) #5 llvm::JumpThreadingPass::ProcessBlock(llvm::BasicBlock*) The crash happens while compiling 'lib/Analysis/CallGraph.cpp'. r3340413 is reverted due to conflicting changes. llvm-svn: 330416
* [NFC][InstCombine] Regenerate two tests that are affected by folding masked ↵Roman Lebedev2018-04-202-71/+71
| | | | | | merge llvm-svn: 330415
* [DebugInfo] Fix for split dwarf test on Windows (NFC)Andrew Ng2018-04-201-1/+1
| | | | | | | | | On Windows, %llc_dwarf automatically adds -mtriple causing this test to error. Changed %llc_dwarf to llc. Differential Revision: https://reviews.llvm.org/D45869 llvm-svn: 330414
* [LTO] Add stats-file option to LTO/Config.h.Florian Hahn2018-04-202-0/+46
| | | | | | | | | | | | | This patch adds a StatsFile option to LTO/Config.h and updates both LLVMGold and llvm-lto2 to set it. Reviewers: MatzeB, tejohnson, espindola Reviewed By: tejohnson Differential Revision: https://reviews.llvm.org/D45531 llvm-svn: 330411
* [AArch64][SVE] Fix diagnostic for SVE LD4 instructions:Sander de Smalen2018-04-204-16/+16
| | | | | | | | | | Diagnostic: 'index must be multiple of 3 in range [-32, 28]' Must be: 'index must be multiple of 4 in range [-32, 28]' llvm-svn: 330407
* Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.Michael Zolotukhin2018-04-201-0/+28
| | | | | | | | | Hopefully, changing set to vector removes nondeterminism detected by some bots, or the new assert will catch something. This reverts commit r330180. llvm-svn: 330403
* Revert "This pass, fixing an erratum in some LEON 2 processors..."Daniel Cederman2018-04-201-11/+0
| | | | | | | | | | | | | | | | | | | | | Summary: Reading Atmel's AT697E errata document this does not seem like a valid workaround. While the text only mentions SDIV, it says that the ICC flags can be wrong, and those are only generated by SDIVcc. Verification on hardware shows that simply replacing SDIV with SDIVcc does not avoid the bug with negative operands. This reverts r283727. Reviewers: lero_chris, jyknight Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45813 llvm-svn: 330397
* [Sparc] Use synthetic instruction clr to zero register instead of sethiDaniel Cederman2018-04-204-4/+51
| | | | | | | | | | | | | | | Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register looks much better than `sethi 0, reg`. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45810 llvm-svn: 330396
* AMDGPU: Legalize the operand of SI_INIT_M0Nicolai Haehnle2018-04-201-0/+15
| | | | | | | | | | | | | | | | | | | | Summary: This fixes a case where the argument to a sendmsg intrinsic ends up in a VGPR, for whatever reason. The underlying performance issue is that a multiplication that can be an s_mul_i32 is instead needlessly generated as v_mul_u32_u24, but this is not addressed by this patch. Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328 Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45826 llvm-svn: 330393
* [Sparc] Fix addressing mode when using 64-bit values in inline assemblyDaniel Cederman2018-04-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a 64-bit register is used as an operand in inline assembly together with a memory reference, the memory addressing will be wrong. The addressing will be a single reg, instead of reg+reg or reg+imm. This will generate a bad offset value or an exception in printMemOperand(). For example: ``` long long int val = 5; long long int mem; __asm__ volatile ("std %1, %0":"=m"(mem):"r"(val)); ``` becomes: ``` std %i0, [%i2+589833] ``` The problem is that SelectInlineAsmMemoryOperand() is never called for the memory references if one of the operands is a 64-bit register. By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc version of SelectInlineAsmMemoryOperand() gets called for each memory reference. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45761 llvm-svn: 330392
* Fix build failures for r330387 on buildbots that don't build the X86 targetVlad Tsyrklevich2018-04-201-0/+3
| | | | llvm-svn: 330388
* LowerTypeTests: Propagate symver directivesVlad Tsyrklevich2018-04-202-0/+38
| | | | | | | | | | | | | | | | | | | | | | Summary: This change fixes https://crbug.com/834474, a build failure caused by LowerTypeTests not preserving .symver symbol versioning directives for exported functions. Emit symver information to ThinLTO summary data and then propagate symver directives for exported functions to the merged module. Emitting symver information to the summaries increases the size of intermediate build artifacts for a Chromium build by less than 0.2%. Reviewers: pcc Reviewed By: pcc Subscribers: tejohnson, mehdi_amini, eraman, llvm-commits, eugenis, kcc Differential Revision: https://reviews.llvm.org/D45798 llvm-svn: 330387
* [llvm-mca][X86] Add prefetch instruction resource testsSimon Pilgrim2018-04-191-1/+14
| | | | llvm-svn: 330371
* [WebAssembly] Enabled -triple=wasm32-unknown-unknown-wasm path using ELF ↵Sam Clegg2018-04-191-0/+1
| | | | | | | | | | | | | | | | directive parser. This is a temporary solution until a proper WASM implementation of MCAsmParserExtension is in place, but at least for now will unblock this path. Added test to make sure this path works with the WASM Assembler. Patch By Wouter van Oortmerssen! Differential Revision: https://reviews.llvm.org/D45386 llvm-svn: 330370
* [Reassociate] add baseline tests for binop swapping; NFCSanjay Patel2018-04-191-0/+286
| | | | | | | | | Similar to rL330086, I don't know if we want to do these transforms here, but we might as well have the tests here either way to show that this pass is missing potential functionality (intentionally or not). llvm-svn: 330368
* [llvm-mca][FMA] Add FMA resource testsSimon Pilgrim2018-04-195-0/+3522
| | | | llvm-svn: 330366
* [AMDGPU] Use packed literals with zero either lower or hi partStanislav Mekhanoshin2018-04-194-5/+98
| | | | | | Differential Revision: https://reviews.llvm.org/D45790 llvm-svn: 330365
* [X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.Craig Topper2018-04-191-3/+5
| | | | | | Silvermont and Goldmont have the same issue on popcnt as Sandy Bridge, Haswell, Broadwell, and Skylake. Believe it is fixed in Goldmont Plus. llvm-svn: 330358
* [PM/LoopUnswitch] Detect irreducible control flow within loops and skip ↵Chandler Carruth2018-04-191-0/+30
| | | | | | | | | | | | | | | | | | | | unswitching non-trivial edges. Summary: This fixes the bug pointed out in review with non-trivial unswitching. This also provides a basis that should make it pretty easy to finish fleshing out a routine to scan an entire function body for irreducible control flow, but this patch remains minimal for disabling loop unswitch. Reviewers: sanjoy, fedor.sergeev Subscribers: mcrosier, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45754 llvm-svn: 330357
* [llvm-mca][X86] Add resource test for every out-of-order scheduler modelSimon Pilgrim2018-04-197-0/+14536
| | | | | | | | | | I've copied and regenerated a resource file from btver2 to every x86 scheduler model supported by llvm-mca so we have at least some basic coverage. For most this has been the avx1 tests, but for silvermont I've used sse42 as thats the latest it supports. More will be added later. llvm-svn: 330352
* [X86] Correct the scheduling data for register forms of XCHG and XADD on ↵Craig Topper2018-04-192-76/+76
| | | | | | | | | | | | Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
* [if-converter] Handle BBs that terminate in ret during diamond conversionKrzysztof Parzyszek2018-04-192-0/+59
| | | | | | | | | | This fixes https://llvm.org/PR36825. Original patch by Valentin Churavy (D45218). Differential Revision: https://reviews.llvm.org/D45731 llvm-svn: 330345
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+34
| | | | llvm-svn: 330344
* [llvm-objdump] Remove test object fileFrancis Visoiu Mistrih2018-04-191-0/+0
| | | | | | Forgot to remove it from the previous commit. llvm-svn: 330343
* [llvm-objdump] Print "..." instead of random data for virtual sectionsFrancis Visoiu Mistrih2018-04-192-0/+9
| | | | | | | | | | | | | | | | | When disassembling with -D, skip virtual sections by printing "..." for each symbol. This patch also implements `MachOObjectFile::isSectionVirtual`. Test case comes from: ``` .zerofill __DATA,__common,_data64unsigned,472,3 ``` Differential Revision: https://reviews.llvm.org/D45824 llvm-svn: 330342
OpenPOWER on IntegriCloud