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* Fix .comm and .lcomm on COFF.Rafael Espindola2013-11-251-0/+25
| | | | | | | | | | | | | | | | These should not use COMDATs. GNU as uses .bss for .lcomm and section 0 for .comm. Given static int a; int b; MSVC puts both in .bss. This patch then puts both .comm and .lcomm on .bss. With this change we agree with gas on .lcomm, are much closer on .comm and clang-cl matches msvc on the above example. llvm-svn: 195654
* [ARM] Enable FeatureMP for Cortex-A5 by default.Amara Emerson2013-11-251-1/+44
| | | | | | Patch by Oliver Stannard. llvm-svn: 195640
* Revert r195599 as it broke the builds.Amara Emerson2013-11-251-29/+0
| | | | llvm-svn: 195636
* Fixed tryFoldToZero() for vector types that need expansion.Daniel Sanders2013-11-251-0/+143
| | | | | | | | | | | | | | | | | | | | | | Summary: Moved the requirement for SelectionDAG::getConstant() to return legally typed nodes slightly earlier. There were two optional DAGCombine passes that were missed out and were required to produce type-legal DAGs. Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant(). This provides support for both promoted and expanded vector types whereas the previous code only supported promoted vector types. Fixes a "Type for zero vector elements is not legal" assertion detected by an llvm-stress generated test. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2251 llvm-svn: 195635
* Don't look past volatile loads.Bill Wendling2013-11-251-0/+29
| | | | | | | A volatile load should block us from trying to coalesce stores. PR18023 llvm-svn: 195599
* Fixed a bug about disassembling AArch64 post-index load/store single element ↵Hao Liu2013-11-251-7/+7
| | | | | | | | | | instructions. ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble will be disassembled into the same instruction st1 {v0b}[0], [x0], x0. llvm-svn: 195591
* [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of ↵Venkatraman Govindaraju2013-11-241-0/+21
| | | | | | sethi+or. This generates correct code for both sparc32 and sparc64. llvm-svn: 195576
* [SparcV9]: Do not emit .register directives for global registers that are ↵Venkatraman Govindaraju2013-11-241-2/+0
| | | | | | clobbered by calls but not used in the function itself. llvm-svn: 195574
* [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.Venkatraman Govindaraju2013-11-241-6/+16
| | | | llvm-svn: 195573
* Make sure that for C++ emitting LwConstant32 pseudos, that it correspondsReed Kotler2013-11-241-1/+3
| | | | | | | | | | to what is needed for constant islands. The prescan method for Mips16 constant islands will eventually go away. It is only temporary and should be done earlier when the instructions are first created or from the DAG. If we keep it here we need to handle better the situation where constant islands is called multiple times since don't want to prescan more than once. llvm-svn: 195569
* Update older test cases for latest patch.Reed Kotler2013-11-242-2/+2
| | | | llvm-svn: 195566
* Fix a funny bug I introduced during conversion of ARM constant islands to Mips.Reed Kotler2013-11-241-0/+39
| | | | | | | | | | | | I had to move some code and I moved a declaration forward past it's first use in the function but by nutty coincidence there was another variable of the same name and type and with completely unrelated function that was declared globally in the class so no compilation error ensued. It required some unusual conditions for it to even matter. Caused test case casts.c in test-suite to fail during compilation with a duplicate symbol error. I would have noticed it during final code review for this port. llvm-svn: 195565
* Debug Info: update testing cases to specify the debug info version number.Manman Ren2013-11-2310-16/+49
| | | | | | | | | | We are going to drop debug info without a version number or with a different version number, to make sure we don't crash when we see bitcode files with different debug info metadata format. Make tests more robust by removing hard-coded metadata numbers in CHECK lines. llvm-svn: 195535
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-222-9/+577
| | | | | | | | We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195514
* Debug Info: update testing cases to specify the debug info version number.Manman Ren2013-11-22206-127/+489
| | | | | | | | We are going to drop debug info without a version number or with a different version number, to make sure we don't crash when we see bitcode files with different debug info metadata format. llvm-svn: 195504
* X86: Perform integer comparisons at i32 or larger.Jim Grosbach2013-11-226-106/+21
| | | | | | | | | | | | | | | Utilizing the 8 and 16 bit comparison instructions, even when an input can be folded into the comparison instruction itself, is typically not worth it. There are too many partial register stalls as a result, leading to significant slowdowns. By always performing comparisons on at least 32-bit registers, performance of the calculation chain leading to the comparison improves. Continue to use the smaller comparisons when minimizing size, as that allows better folding of loads into the comparison instructions. rdar://15386341 llvm-svn: 195496
* StructurizeCFG: Fix verification failure with some loops.Matt Arsenault2013-11-221-0/+31
| | | | | | | | | If the beginning of the loop was also the entry block of the function, branches were inserted to the entry block which isn't allowed. If this occurs, create a new dummy function entry block that branches to the start of the loop. llvm-svn: 195493
* StructurizeCFG: Fix inverting a branch on an argumentMatt Arsenault2013-11-221-0/+47
| | | | llvm-svn: 195492
* Teach ISel not to optimize 'optnone' functions (revised).Paul Robinson2013-11-221-0/+42
| | | | | | | | | | | | | Improvements over r195317: - Set/restore EnableFastISel flag instead of just running FastISel within SelectAllBasicBlocks; the flag is checked in various places, and FastISel won't run properly if those places don't do the right thing. - Test looks for normal ISel versus FastISel behavior, and not something more subtle that doesn't work everywhere. Based on work by Andrea Di Biagio. llvm-svn: 195491
* patchpoint: factor SD builder code for live vars. Plain stackmap also ↵Andrew Trick2013-11-221-1/+19
| | | | | | optimizes Constant values now. llvm-svn: 195488
* Add a fixed version of r195470 back.Rafael Espindola2013-11-221-5/+6
| | | | | | | | | | | | | | | | The fix is simply to use CurI instead of I when handling aliases to avoid accessing a invalid iterator. original message: Convert linkonce* to weak* instead of strong. Also refactor the logic into a helper function. This is an important improve on mingw where the linker complains about mixed weak and strong symbols. Converting to weak ensures that the symbol is not dropped, but keeps in a comdat, making the linker happy. llvm-svn: 195477
* Fix PR18014Michael Liao2013-11-221-0/+16
| | | | | | | - When simplifying the mask generation for BLEND, check whether that mask is also consumed by other non-BLEND insns. If true, skip that simplification. llvm-svn: 195476
* [SystemZ] Fix TMHH and TMHL usage for z10 with -O0Richard Sandiford2013-11-222-0/+50
| | | | | | | | | | | | I've no idea why I decided to handle TMxx differently from all the other high/low logic operations, but it was a stupid thing to do. The high registers aren't available as separate 32-bit registers on z10, so subreg_h32 can't be used on a GR64 there. I've normally been testing with z196 and with -O3 and so hadn't noticed this until now. llvm-svn: 195473
* Revert "Convert linkonce* to weak* instead of strong."Rafael Espindola2013-11-221-6/+5
| | | | | | | This reverts commit r195470. Debugging failure in some bots. llvm-svn: 195472
* Add a Scalarizer pass.Richard Sandiford2013-11-223-0/+500
| | | | llvm-svn: 195471
* Convert linkonce* to weak* instead of strong.Rafael Espindola2013-11-221-5/+6
| | | | | | | | | Also refactor the logic into a helper function. This is an important improvement on mingw where the linker complains about mixed weak and strong symbols. Converting to weak ensures that the symbol is not dropped, but keeps in a comdat, making the linker happy. llvm-svn: 195470
* [mips][msa] Add test case that should have been added in r195456.Daniel Sanders2013-11-221-0/+31
| | | | llvm-svn: 195469
* Don't produce tail calls when the caller is x86_thiscallcc.Rafael Espindola2013-11-221-0/+8
| | | | | | The callee will not pop the stack for us. llvm-svn: 195467
* ARM: use CHECK-LABEL on a test.Tim Northover2013-11-221-20/+20
| | | | llvm-svn: 195457
* Add support for Cortex-A12.Richard Barton2013-11-221-0/+32
| | | | | | Patch by Oliver Stannard! llvm-svn: 195448
* [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast ↵Daniel Sanders2013-11-221-0/+27
| | | | | | | | from the appropriate integer vector type. Fixes an instruction selection failure detected by llvm-stress. llvm-svn: 195444
* Revert r195318 as it causes miscompilation (PR18029)Kostya Serebryany2013-11-222-4/+6
| | | | llvm-svn: 195439
* Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 ↵Hao Liu2013-11-222-0/+155
| | | | | | | | | and vector types. e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. "%tmp = bitcast i64 %in to <2 x i32>" can't be selected. llvm-svn: 195424
* For AArch64 back-end instruction selection, lower Neon_Lowxxx with ↵Jiangning Liu2013-11-221-42/+42
| | | | | | EXTRCT_SUBREG. llvm-svn: 195408
* Tweak 3 tests in llvm/test/CodeGen/X86 to add -mcpu=generic since r195383.NAKAMURA Takumi2013-11-223-3/+3
| | | | | | | They failed on bdver2 buildslave. FIXME: FileCheck-ize them. llvm-svn: 195407
* SLP Vectorizer: Extract cost will only be added once even if the scalar has ↵Yi Jiang2013-11-221-0/+30
| | | | | | multiple external uses. llvm-svn: 195406
* SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_typeTom Stellard2013-11-221-0/+15
| | | | | | | | | The legalizer can now do this type of expansion for more type combinations without loading and storing to and from the stack. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195398
* In Dwarf 3 (and Dwarf 2) attributes whose value are offsets into aEric Christopher2013-11-215-41/+158
| | | | | | | | | | | | | | | | | | | | | section use the form DW_FORM_data4 whilst in Dwarf 4 and later they use the form DW_FORM_sec_offset. This patch updates the places where such attributes are generated to use the appropriate form depending on the Dwarf version. The DIE entries affected have the following tags: DW_AT_stmt_list, DW_AT_ranges, DW_AT_location, DW_AT_GNU_pubnames, DW_AT_GNU_pubtypes, DW_AT_GNU_addr_base, DW_AT_GNU_ranges_base It also adds a hidden command line option "--dwarf-version=<uint>" to llc which allows the version of Dwarf to be generated to override what is specified in the metadata; this makes it possible to update existing tests to check the debugging information generated for both Dwarf 4 (the default) and Dwarf 3 using the same metadata. Patch (slightly modified) by Keith Walker! llvm-svn: 195391
* SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency ↵Ekaterina Romanova2013-11-214-0/+275
| | | | | | | | | | on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction. AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. llvm-svn: 195383
* Introduce two command-line flags for the instrumentation pass to control ↵Peter Collingbourne2013-11-212-111/+256
| | | | | | | | | | | | | | whether the labels of pointers should be ignored in load and store instructions The new command line flags are -dfsan-ignore-pointer-label-on-store and -dfsan-ignore-pointer-label-on-load. Their default value matches the current labelling scheme. Additionally, the function __dfsan_union_load is marked as readonly. Patch by Lorenzo Martignoni! Differential Revision: http://llvm-reviews.chandlerc.com/D2187 llvm-svn: 195382
* [ARM] add the overlooked tests for Cortex-A7 build attributesArtyom Skrobov2013-11-211-0/+75
| | | | llvm-svn: 195365
* [mips][msa] Fix a corner case in performORCombine() when combining nodes ↵Daniel Sanders2013-11-211-0/+33
| | | | | | | | | | | | | | | into VSELECT. Mask == ~InvMask asserts if the width of Mask and InvMask differ. The combine isn't valid (with two exceptions, see below) if the widths differ so test for this before testing Mask == ~InvMask. In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and InvMask=~0, the combine is still valid. However, there are more appropriate combines that could be used in these cases such as folding x & 0 to 0, or x & ~0 to x. llvm-svn: 195364
* Add support for legalizing SETNE/SETEQ by inverting the condition code and ↵Daniel Sanders2013-11-212-0/+234
| | | | | | | | | | | | | | | | | | | | | | | | | the result of the comparison. Summary: LegalizeSetCCCondCode can now legalize SETEQ and SETNE by returning the inverse condition and requesting that the caller invert the result of the condition. The caller of LegalizeSetCCCondCode must handle the inverted CC, and they do so as follows: SETCC, BR_CC: Invert the result of the SETCC with SelectionDAG::getNOT() SELECT_CC: Swap the true/false operands. This is necessary for MSA which lacks an integer SETNE instruction. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2229 llvm-svn: 195355
* [msan] Propagate condition origin in select instruction.Evgeniy Stepanov2013-11-211-0/+7
| | | | llvm-svn: 195349
* [mips][msa/dsp] Only do DSP combines if DSP is enabled.Daniel Sanders2013-11-211-0/+141
| | | | | | Fixes a crash (null pointer dereferenced) when MSA is enabled. llvm-svn: 195343
* Use multiple filecheck prefixes in msan instrumentation tests.Evgeniy Stepanov2013-11-212-72/+57
| | | | llvm-svn: 195342
* Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."NAKAMURA Takumi2013-11-211-32/+0
| | | | | | | | It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown". FYI, it didn't appear to add either "-O0" or "-fast-isel". llvm-svn: 195339
* add 'REQUIRES: asserts' to a test that uses 'llc -debug'; this fixes the ↵Kostya Serebryany2013-11-211-0/+1
| | | | | | no-asserts build llvm-svn: 195333
* Implemented Neon scalar vdup_lane intrinsics.Ana Pazos2013-11-212-0/+106
| | | | | | Fixed scalar dup alias and added test case. llvm-svn: 195330
* Implemented Neon scalar by element intrinsics.Ana Pazos2013-11-212-70/+37
| | | | | | | Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane, vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics. llvm-svn: 195327
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