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* [X86] Change PMULLD to 10 cycles on Skylake per Agner's tables and ↵Craig Topper2018-03-203-9/+9
| | | | | | | | | | llvm-exegesis. Also restrict to port 0 and 1 for SkylakeClient. It looks like the scheduler models don't account for client not having a full vector ALU on port 5 like server. Fixes PR36808. llvm-svn: 328061
* [MustExecute] Shwo the effect of using full loop info variantPhilip Reames2018-03-201-1/+6
| | | | | | | | Most basic possible test for the logic used by LICM. Also contains a speculative build fix for compiles which complain about a definition of a stuct K; followed by a declaration as class K; llvm-svn: 328058
* [MustExecute] Add simplest possible test for LoopSafetyOnfoPhilip Reames2018-03-201-0/+26
| | | | | | (Currently showing without, will enable and check in diff to show impact) llvm-svn: 328056
* [WebAssembly] Strip threadlocal attribute from globals in single thread modeDerek Schuff2018-03-201-0/+17
| | | | | | | | | The default thread model for wasm is single, and in this mode thread-local global variables can be lowered identically to non-thread-local variables. Differential Revision: https://reviews.llvm.org/D44703 llvm-svn: 328049
* [ObjCARC] Add funclet token to ARC markerShoaib Meenai2018-03-201-0/+61
| | | | | | | | | | | | | | | The inline assembly generated for the ARC autorelease elision marker must have a funclet token if it's emitted inside a funclet, otherwise the inline assembly (and all subsequent code in the funclet) will be marked unreachable by WinEHPrepare. Note that this only applies for the non-O0 case, since at O0, clang emits the autorelease elision marker itself rather than deferring to the backend. The fix for clang is handled in a separate change. Differential Revision: https://reviews.llvm.org/D44641 llvm-svn: 328042
* [X86] Don't use the MSVC stack protector names on mingwMartin Storsjo2018-03-202-1/+200
| | | | | | | | | | | Mingw uses the same stack protector functions as GCC provides on other platforms as well. Patch by Valentin Churavy! Differential Revision: https://reviews.llvm.org/D27296 llvm-svn: 328039
* For llvm-objdump and Mach-O files, fix the printing of module init andKevin Enderby2018-03-202-0/+4
| | | | | | | | | | | term sections from .o files to look to see if the pointers have a relocation entry and if so print the symbol name from the relocation entry. If not fall back to the existing code and use the pointer value to look up that value in the symbol table. rdar://38337506 llvm-svn: 328037
* [AArch64] Add vmulxh_lane fp16 vector intrinsicAbderrazek Zaafrani2018-03-201-0/+30
| | | | | | https://reviews.llvm.org/D44591 llvm-svn: 328035
* [DEBUGINFO] Add -no-dwarf-debug-ranges option.Alexey Bataev2018-03-201-0/+54
| | | | | | | | | | | | | | Summary: Added option -no-dwarf-debug-ranges option to disable emission of .debug_ranges section. Reviewers: probinson, echristo Subscribers: aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D44384 llvm-svn: 328030
* [WebAssembly] Added initial AsmParser implementation.Derek Schuff2018-03-201-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It uses the MC framework and the tablegen matcher to do the heavy lifting. Can handle both explicit and implicit locals (-disable-wasm-explicit-locals). Comes with a small regression test. This is a first basic implementation that can parse most llvm .s output and round-trips most instructions succesfully, but in order to keep the commit small, does not address all issues. There are a fair number of mismatches between what MC / assembly matcher think a "CPU" should look like and what WASM provides, some already have workarounds in this commit (e.g. the way it deals with register operands) and some that require further work. Some of that further work may involve changing what the Disassembler outputs (and what s2wasm parses), so are probably best left to followups. Some known things missing: - Many directives are ignored and not emitted. - Vararg calls are parsed but extra args not emitted. - Loop signatures are likely incorrect. - $drop= is not emitted. - Disassembler does not output SIMD types correctly, so assembler can't test them. Patch by Wouter van Oortmerssen Differential Revision: https://reviews.llvm.org/D44329 llvm-svn: 328028
* [llvm-objcopy] Revert the tests from r328012Alexander Shaposhnikov2018-03-204-152/+0
| | | | | | Temporarily revert the tests from r328012 as well. llvm-svn: 328026
* [Hexagon] Add a few more lit tests, NFCKrzysztof Parzyszek2018-03-2014-0/+1134
| | | | llvm-svn: 328023
* [Hexagon] Add heuristic to exclude critical path cost for schedulingKrzysztof Parzyszek2018-03-204-7/+9
| | | | | | Patch by Brendon Cahoon. llvm-svn: 328022
* [PowerPC][LegalizeFloatTypes] Move the PPC hacks for (i32 ↵Craig Topper2018-03-201-1/+318
| | | | | | | | | | | | | | fp_to_sint/fp_to_uint (ppcf128 X)) out of LegalizeFloatTypes and into PPC specific code I'm not entirely sure these hacks are still needed. If you remove the hacks completely, the name of the library call that gets generated doesn't match the grep the test previously had. So the test wasn't really checking anything. If the hack is still needed it belongs in PPC specific code. I believe the FP_TO_SINT code here is the only place in the tree where a FP_ROUND_INREG node is created today. And I don't think its even being used correctly because the legalization returned a BUILD_PAIR with the same value twice. That doesn't seem right to me. By moving the code entirely to PPC we can avoid creating the FP_ROUND_INREG at all. I replaced the grep in the existing test with full checks generated by hacking update_llc_test_check.py to support ppc32 just long enough to generate it. Differential Revision: https://reviews.llvm.org/D44061 llvm-svn: 328017
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-03-205-5/+5
| | | | | | | | | | | | | | | | | Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters that cover the low halves of these registers. This change adds artificial subregisters for the high halves in order to differentiate (in terms of register units) between the 32- and the low 16-bit registers. This patch contains parts that aim to preserve the calculated register pressure. This is in order to preserve the current codegen (minimize the impact of this patch). The approach of having artificial subregisters could be used to fix PR23423, but the pressure calculation would need to be changed. Differential Revision: https://reviews.llvm.org/D43353 llvm-svn: 328016
* [MustExecute] Use the annotation style printerPhilip Reames2018-03-201-21/+28
| | | | | | | As suggested in the original review (https://reviews.llvm.org/D44524), use an annotation style printer instead. Note: The switch from -analyze to -disable-output in tests was driven by the fact that seems to be the idiomatic style used in annoation passes. I tried to keep both working, but the old style pass API for printers really doesn't make this easy. It invokes (runOnFunction, print(Module)) repeatedly. I decided the extra state wasn't worth it given the old pass manager is going away soonish anyway. llvm-svn: 328015
* [llvm-objcopy] Implement support for section groupsAlexander Shaposhnikov2018-03-204-0/+152
| | | | | | | | | | | | | | | | | This diff adds support for SHT_GROUP sections to llvm-objcopy. Some sections are interrelated and comprise a group. For example, a definition of an inline function might require, in addition to the section containing its instructions, a read-only data section containing literals referenced inside the function. A section of the type SHT_GROUP contains the indices of the group members, therefore, it needs to be updated whenever the indices change. Similarly, the fields sh_link, sh_info should be recalculated as well. Test plan: make check-all Differential revision: https://reviews.llvm.org/D43996 llvm-svn: 328012
* [NVPTX] Make tensor load/store intrinsics overloaded.Artem Belevich2018-03-201-16/+36
| | | | | | | | | | | | | | | | This way we can support address-space specific variants without explicitly encoding the space in the name of the intrinsic. Less intrinsics to deal with -> less boilerplate. Added a bit of tablegen magic to match/replace an intrinsics with a pointer argument in particular address space with the space-specific instruction variant. Updated tests to use non-default address spaces. Differential Revision: https://reviews.llvm.org/D43268 llvm-svn: 328006
* Add an analysis printer for must execute reasoningPhilip Reames2018-03-201-0/+80
| | | | | | | | | | | | Many of our loop passes make use of so called "must execute" or "guaranteed to execute" facts to prove the legality of code motion. The basic notion is that we know (by assumption) an instruction didn't fault at it's original location, so if the location we move it to is strictly post dominated by the original, then we can't have introduced a new fault. At the moment, the testing for this logic is somewhat adhoc and done mostly through LICM. Since I'm working on that code, I want to improve the testing. This patch is the first step in that direction. It doesn't actually test the variant used by the loop passes - I need to move that to the Analysis library first - but instead exercises an alternate implementation used by SCEV. (I plan on merging both implementations.) Note: I'll be replacing the printing logic within this with an annotation based version in the near future. Anna suggested this in review, and it seems like a strictly better format. Differential Revision: https://reviews.llvm.org/D44524 llvm-svn: 328004
* [Hexagon] Correct the computation of TopReadyCycle and BotReadyCycle of SUKrzysztof Parzyszek2018-03-201-1/+0
| | | | | | | | | TopReadyCycle and BotReadyCycle were off by one cycle when an SU is either the first instruction or the last instruction in a packet. Patch by Ikhlas Ajbar. llvm-svn: 328000
* [XRay] Lazily compute MachineLoopInfo instead of requiring it.Michael Zolotukhin2018-03-201-2/+0
| | | | | | | | | | | | | | | | Summary: Currently X-Ray Instrumentation pass has a dependency on MachineLoopInfo (and thus on MachineDominatorTree as well) and we have to compute them even if X-Ray is not used. This patch changes it to a lazy computation to save compile time by avoiding these redundant computations. Reviewers: dberris, kubamracek Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D44666 llvm-svn: 327999
* [AArch64] add fabs tests for PR36600; NFCSanjay Patel2018-03-201-0/+33
| | | | llvm-svn: 327995
* [DEBUGINFO] Add flag -no-dwarf-pub-sections to disable pub sections.Alexey Bataev2018-03-201-0/+31
| | | | | | | | | | | | | | Summary: Added a flag -no-dwarf-pub-sections, which allows to disable emission of DWARF public sections. Reviewers: probinson, echristo Subscribers: aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D44385 llvm-svn: 327994
* [X86][Haswell][Znver1] Fix typo in fldl instregexsSimon Pilgrim2018-03-201-6/+6
| | | | | | | | Missing comma was casing 2 instregex entries to be concatenated together by mistake. Found while investigating PR35548 llvm-svn: 327992
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-202-0/+111
| | | | | | | As part of this, add support for load/store from the constant pool. This is used to materialise f32 constants. llvm-svn: 327979
* [RISCV] Add codegen for RV32F arithmetic and conversion operationsAlex Bradbury2018-03-202-0/+262
| | | | | | Currently, only a soft floating point ABI is supported. llvm-svn: 327976
* [Hexagon] Improve scheduling based on register pressureKrzysztof Parzyszek2018-03-203-5/+7
| | | | | | Patch by Brendon Cahoon. llvm-svn: 327975
* [MergeICmp] Fix a bug in entry block shuffled to middle of the chainXin Tong2018-03-202-1/+58
| | | | | | | | | | | | Summary: Fix a bug in entry block shuffled to middle of the chain. Reviewers: davide, courbet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44642 llvm-svn: 327971
* [AVR] Add a regression test for struct return loweringDylan McKay2018-03-201-0/+21
| | | | | | | | | | | | The test is taken from https://github.com/avr-rust/rust/issues/57 The originally implementation of struct return lowering was made in r325474. Patch by Peter Nimmervoll llvm-svn: 327967
* [LV] Let recordVectorLoopValueForInductionCast to check if IV was created ↵Andrei Elovikov2018-03-201-0/+39
| | | | | | | | | | | | | | | | | | | | | | from the cast. Summary: It turned out to be error-prone to expect the callers to handle that - better to leave the decision to this routine and make the required data to be explicitly passed to the function. This handles the case that was missed in the r322473 and fixes the assert mentioned in PR36524. Reviewers: dorit, mssimpso, Ayal, dcaballe Reviewed By: dcaballe Subscribers: Ka-Ka, hiraditya, dneilson, hsaito, llvm-commits Differential Revision: https://reviews.llvm.org/D43812 llvm-svn: 327960
* [SystemZ] Add "REQUIRES: asserts" to test case to fix build bots.Jonas Paulsson2018-03-201-0/+1
| | | | llvm-svn: 327958
* [X86] Properly implement the calling convention for f80 for mingw/x86_64Martin Storsjo2018-03-203-31/+102
| | | | | | | | | | | | | | | | In these cases, both parameters and return values are passed as a pointer to a stack allocation. MSVC doesn't use the f80 data type at all, while it is used for long doubles on mingw. Normally, this part of the calling convention is handled within clang, but for intrinsics that are lowered to libcalls, it may need to be handled within llvm as well. Differential Revision: https://reviews.llvm.org/D44592 llvm-svn: 327957
* [X86] Fix the SchedRW for memory forms of CMP and TEST.Craig Topper2018-03-201-38/+38
| | | | | | | | They were incorrectly marked as RMW operations. Some of the CMP instrucions worked, but the ones that use a similar encoding as RMW form of ADD ended up marked as RMW. TEST used the same tablegen class as some of the CMPs. llvm-svn: 327947
* [X86] Add TEST16mi/TEST32mi/TEST64mi32 to the ↵Craig Topper2018-03-201-28/+28
| | | | | | | | Sandybridge/Haswell/Broadwell/Skylake scheduler models. Move it from a load+store group on SNB to a load only group, the same group as CMP. llvm-svn: 327944
* [X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.Craig Topper2018-03-201-48/+48
| | | | | | I assume these match the generic immediate version like they do in the other models. llvm-svn: 327943
* [ShrinkWrap] Take into account landing padQuentin Colombet2018-03-201-0/+102
| | | | | | | | | | | | | When scanning the function for CSRs uses and defs, also check if the basic block are landing pads. Consider that landing pads needs the CSRs to be properly set. That way we force the prologue/epilogue to always be pushed out of the problematic "throw" region. The "throw" region is problematic because the jumps are not properly modeled. Fixes PR36513 llvm-svn: 327942
* [RISCV] Preserve stack space for outgoing arguments when the function ↵Shiva Chen2018-03-202-7/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | contain variable size objects E.g. bar (int x) { char p[x]; push outgoing variables for foo. call foo } We need to generate stack adjustment instructions for outgoing arguments by eliminateCallFramePseudoInstr when the function contains variable size objects to avoid outgoing variables corrupt the variable size object. Default hasReservedCallFrame will return !hasFP(). We don't want to generate extra sp adjustment instructions when hasFP() return true, So We override hasReservedCallFrame as !hasVarSizedObjects(). Differential Revision: https://reviews.llvm.org/D43752 llvm-svn: 327938
* [X86] Fix the SNB scheduler for BLENDVB.Craig Topper2018-03-201-2/+2
| | | | | | PBLENDVBrr0 was with the memory version of VBLENDVB and PBLENDVBrm0 was missing. llvm-svn: 327937
* Run dos2unix on a test. NFC.Rafael Espindola2018-03-201-30/+30
| | | | llvm-svn: 327934
* Object: Fix handling of @@@ in .symver directiveVitaly Buka2018-03-201-0/+40
| | | | | | | | | | | | | | | | | Summary: name@@@nodename is going to be replaced with name@@nodename if symbols is defined in the assembled file, or name@nodename if undefined. https://sourceware.org/binutils/docs/as/Symver.html Fixes PR36623 Reviewers: pcc, espindola Subscribers: mehdi_amini, hiraditya Differential Revision: https://reviews.llvm.org/D44274 llvm-svn: 327930
* [SelectionDAG] Transfer DbgValues when integer operations are promotedAaron Smith2018-03-192-4/+64
| | | | | | | | | | | | | | | | | | | | | Summary: DbgValue nodes were not transferred when integer DAG nodes were promoted. For example, if an i32 add node was promoted to an i64 add node by DAGTypeLegalizer::PromoteIntegerResult(), its DbgValue node was not transferred to the new node. The simple fix is to update SetPromotedInteger() to transfer DbgValues. Add AArch64/dbg-value-i8.ll to test this change and fix ARM/debug-info-d16-reg.ll which had the wrong DILocalVariable nodes with arg numbers even though they are not for function parameters. Patch by Se Jong Oh! Reviewers: vsk, JDevlieghere, aprantl Reviewed By: JDevlieghere Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D44546 llvm-svn: 327919
* [MachineOutliner] AArch64: Emit CFI instructions when outlining callsJessica Paquette2018-03-191-0/+67
| | | | | | | | | | | When outlining calls, the outliner needs to update CFI to ensure that, say, exception handling works. This commit adds that functionality and adds a test just for call outlining. Call outlining stuff in machine-outliner.mir should be moved into machine-outliner-calls.mir in a later commit. llvm-svn: 327917
* [Hexagon] Add REQUIRES: asserts to test/CodeGen/Hexagon/v6vec_inc1.llKrzysztof Parzyszek2018-03-191-0/+1
| | | | llvm-svn: 327907
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-1915-383/+323
| | | | | | | Reland ISel cycle checking improvements after simplifying node id invariant traversal and correcting typo. llvm-svn: 327898
* [ARM, AArch64] Check the no-stack-arg-probe attribute for dynamic stack probesMartin Storsjo2018-03-194-0/+62
| | | | | | | | | | | | | This extends the use of this attribute on ARM and AArch64 from SVN r325900 (where it was only checked for fixed stack allocations on ARM/AArch64, but for all stack allocations on X86). This also adds a testcase for the existing use of disabling the fixed stack probe with the attribute on ARM and AArch64. Differential Revision: https://reviews.llvm.org/D44291 llvm-svn: 327897
* [AMDGPU] change test to avoid NaN mathSanjay Patel2018-03-191-1/+1
| | | | llvm-svn: 327891
* [AMDGPU] adjust tests to be nan-freeSanjay Patel2018-03-193-51/+60
| | | | | | | | As suggested in D44521 - bitcast to integer for the math, so we preserve the intent of these tests when NaN math gets folded away. llvm-svn: 327890
* [Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrtLei Huang2018-03-191-0/+76
| | | | | | | | | | | | | | Legalize and emit code for quad-precision floating point operations: * xscpsgnqp * xsabsqp * xsnabsqp * xsnegqp * xssqrtqp Differential Revision: https://reviews.llvm.org/D44530 llvm-svn: 327889
* [Hexagon] Add a few more lit testsKrzysztof Parzyszek2018-03-1918-1/+1652
| | | | llvm-svn: 327884
* [X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge scheduler model.Craig Topper2018-03-191-8/+8
| | | | | | PR35590 was already filed for this information being wrong. It's probably better to default to WriteSystem behavior instead of using something completely wrong. llvm-svn: 327882
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