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* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-311-0/+83
| | | | llvm-svn: 138845
* Fix test typo.Benjamin Kramer2011-08-311-1/+1
| | | | llvm-svn: 138843
* Remove the old tail duplication pass. It is not used and is unable to updateRafael Espindola2011-08-3014-261/+2
| | | | | | | ssa, so it has to be run really early in the pipeline. Any replacement should probably use the SSAUpdater. llvm-svn: 138841
* Fix issues with disassembly of IT instructions involving condition codes ↵Owen Anderson2011-08-301-0/+12
| | | | | | other the EQ/NE. Discovered by roundtrip testing. llvm-svn: 138840
* Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather ↵Owen Anderson2011-08-301-0/+9
| | | | | | than labels. llvm-svn: 138837
* Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets ↵Owen Anderson2011-08-301-1/+4
| | | | | | instead of labels. llvm-svn: 138835
* Fix encoding of Thumb1 B instructions with immediate offsets, which is ↵Owen Anderson2011-08-301-1/+4
| | | | | | necessary for round-tripping. llvm-svn: 138834
* Add a triple.Rafael Espindola2011-08-301-2/+2
| | | | llvm-svn: 138831
* Remove empty file.Owen Anderson2011-08-301-0/+0
| | | | llvm-svn: 138830
* Speculatively revert r138809 in an attempt to fix DragonEgg.Owen Anderson2011-08-301-27/+0
| | | | llvm-svn: 138829
* Port Thumb2 assembler tests over to disassembler tests.Owen Anderson2011-08-301-0/+41
| | | | llvm-svn: 138822
* Some test code to check if correct code is being generated.Rafael Espindola2011-08-301-0/+87
| | | | | | Patch by Sanjoy Das. llvm-svn: 138820
* When walking backwards to eliminate final stores to allocas at the end of a ↵Owen Anderson2011-08-301-0/+27
| | | | | | function, encountering an unrelated store should not cause us to give up like encountering a load does. llvm-svn: 138809
* Lit option for ignoring stderr output.Andrew Trick2011-08-301-0/+3
| | | | | | | | This is useful for testing a build a temporarily hand instrumented build. Patch by arrowdodger! llvm-svn: 138804
* Set CR1EQ only when lowering vararg floating arguments (not any varargRoman Divacky2011-08-301-0/+18
| | | | | | arguments as before), unset CR1EQ otherwise. llvm-svn: 138802
* Add vvvv support to disassembling of instructions with MRMDestMem and ↵Craig Topper2011-08-301-0/+3
| | | | | | MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. llvm-svn: 138795
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-302-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
* Add missing encoding information for some of the GPR<->FP register moves.Owen Anderson2011-08-291-0/+3
| | | | llvm-svn: 138780
* Remove redundant tests from XFAIL'ed test file.Jim Grosbach2011-08-291-11/+0
| | | | llvm-svn: 138779
* Thumb2 assembly parsing and encoding support for ADC(immediate).Jim Grosbach2011-08-291-0/+23
| | | | llvm-svn: 138778
* Remove test file. Superceded by other more exhaustive tests.Jim Grosbach2011-08-291-14/+0
| | | | llvm-svn: 138777
* Thumb2 parsing and encoding for IT blocks.Jim Grosbach2011-08-292-0/+62
| | | | llvm-svn: 138773
* Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217Kevin Enderby2011-08-291-0/+3
| | | | llvm-svn: 138771
* Explicitly zero out parts of a vector which are required to be zero by the ↵Eli Friedman2011-08-291-3/+28
| | | | | | algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. llvm-svn: 138768
* Update tests to new EH model. Add landingpad instructions to landing pads.Bill Wendling2011-08-295-0/+33
| | | | llvm-svn: 138759
* Fixes following the CR by Chris and Duncan:Nadav Rotem2011-08-291-3/+36
| | | | | | | Optimize chained bitcasts of the form A->B->A. Undo r138722 and change isEliminableCastPair to allow this case. llvm-svn: 138756
* Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson2011-08-292-7/+15
| | | | llvm-svn: 138754
* Add testcase for r138746.Owen Anderson2011-08-291-0/+34
| | | | llvm-svn: 138747
* Add support for parsing #-0 on non-memory-operand immediate values, and add ↵Owen Anderson2011-08-291-0/+8
| | | | | | a testcase that necessitates it. llvm-svn: 138739
* Fix PR5329: pay attention to constructor/destructor priorityDuncan Sands2011-08-281-0/+21
| | | | | | | when outputting them. With this, the entire LLVM testsuite passes when built with dragonegg. llvm-svn: 138724
* Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X.Nadav Rotem2011-08-281-0/+14
| | | | llvm-svn: 138722
* Reverted r138652, valgrind doesn't understand obj:*/tblgen.Andrew Trick2011-08-273-0/+3
| | | | llvm-svn: 138703
* Auto upgrade the old EH scheme to use the new one. This is on a trial basis. IfBill Wendling2011-08-272-34/+105
| | | | | | things to disasterously over night, this can be reverted. llvm-svn: 138702
* Update to new EH scheme.Bill Wendling2011-08-271-5/+5
| | | | llvm-svn: 138699
* Cannot have an llvm.eh.exception call in a non-landing pad block.Bill Wendling2011-08-271-2/+0
| | | | llvm-svn: 138698
* Excluding ARM JIT tests until someone can fix this compilation path.Andrew Trick2011-08-2614-0/+14
| | | | llvm-svn: 138676
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-262-1/+13
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* Correct encoding of BL with immediate offset.Owen Anderson2011-08-261-0/+2
| | | | llvm-svn: 138673
* Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman2011-08-261-0/+13
| | | | llvm-svn: 138660
* Revert r138606 until LowerInvoke has been converted to the new EH scheme.Bill Wendling2011-08-261-4/+1
| | | | llvm-svn: 138656
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-261-1/+1
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* valgrind: Always suppress tblgen leaks.Andrew Trick2011-08-263-3/+0
| | | | | | I'll clean up the rest of the XFAIL: vg_leak lines if this works. llvm-svn: 138652
* Don't sink landingpad instructions during ind-var simplification.Bill Wendling2011-08-261-0/+32
| | | | llvm-svn: 138651
* Use %% for literals in RUN lines.Andrew Trick2011-08-267-9/+9
| | | | llvm-svn: 138647
* Support an extension of ARM asm syntax to allow immediate operands to ADR ↵Owen Anderson2011-08-264-1/+20
| | | | | | instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
* We don't care if TableGen leaks memory.Benjamin Kramer2011-08-263-0/+3
| | | | llvm-svn: 138634
* Add a testcase for r138625.Owen Anderson2011-08-261-0/+3
| | | | llvm-svn: 138626
* Fix disassembling of VCVTSD2SICraig Topper2011-08-261-0/+9
| | | | llvm-svn: 138623
* Atomic load/store on ARM/Thumb.Eli Friedman2011-08-261-0/+31
| | | | | | | | | | | | I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
* SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load ↵Benjamin Kramer2011-08-261-0/+87
| | | | | | | | | | or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between. In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side. This shrinks the size of a Release clang by 16k on x86_64. llvm-svn: 138618
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