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| author | Eli Friedman <eli.friedman@gmail.com> | 2011-08-31 00:31:29 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2011-08-31 00:31:29 +0000 |
| commit | c3f9c4a852844d1fc328fbd2da872f5bac51ecf9 (patch) | |
| tree | cfc1bb2e147d10608d905eb66b4613b797825e7a /llvm/test | |
| parent | ebb9bb417558d4c3efe4a71ad96dcb5f34e93482 (diff) | |
| download | bcm5719-llvm-c3f9c4a852844d1fc328fbd2da872f5bac51ecf9.tar.gz bcm5719-llvm-c3f9c4a852844d1fc328fbd2da872f5bac51ecf9.zip | |
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
llvm-svn: 138845
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-64bit.ll | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll new file mode 100644 index 00000000000..186581ca8fb --- /dev/null +++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll @@ -0,0 +1,83 @@ +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s + +define i64 @test1(i64* %ptr, i64 %val) { +; CHECK: test1 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: adds r0, r2 +; CHECK: adc r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw add i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test2(i64* %ptr, i64 %val) { +; CHECK: test2 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: subs r0, r2 +; CHECK: sbc r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw sub i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test3(i64* %ptr, i64 %val) { +; CHECK: test3 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: and r0, r2 +; CHECK: and r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw and i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test4(i64* %ptr, i64 %val) { +; CHECK: test4 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: orr r0, r2 +; CHECK: orr r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw or i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test5(i64* %ptr, i64 %val) { +; CHECK: test5 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: eor r0, r2 +; CHECK: eor r1, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw xor i64* %ptr, i64 %val seq_cst + ret i64 %r +} + +define i64 @test6(i64* %ptr, i64 %val) { +; CHECK: test6 +; CHECK: dmb ish +; CHECK: ldrexd r2, r3 +; CHECK: strexd {{r[0-9]+}}, r0, r1 +; CHECK: cmp +; CHECK: bne +; CHECK: dmb ish + %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst + ret i64 %r +}
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