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* bpf: add " ll" in the LD_IMM64 asmstringYonghong Song2017-09-117-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | This partially revert previous fix in commit f5858045aa0b ("bpf: proper print imm64 expression in inst printer"). In that commit, the original suffix "ll" is removed from LD_IMM64 asmstring. In the customer print method, the "ll" suffix is printed if the rhs is an immediate. For example, "r2 = 5ll" => "r2 = 5ll", and "r3 = varll" => "r3 = var". This has an issue though for assembler. Since assembler relies on asmstring to do pattern matching, it will not be able to distiguish between "mov r2, 5" and "ld_imm64 r2, 5" since both asmstring is "r2 = 5". In such cases, the assembler uses 64bit load for all "r = <val>" asm insts. This patch adds back " ll" suffix for ld_imm64 with one additional space for "#reg = #global_var" case. Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 312978
* Update testcases that are XFAILed on Darwin for llvm-dwarfdump changes.Adrian Prantl2017-09-112-2/+2
| | | | llvm-svn: 312977
* [llvm-cov] Try to fix a test on WindowsVedant Kumar2017-09-111-2/+2
| | | | | | | | | Failing bot: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4791 This looks like another stderr redirection issue. llvm-svn: 312975
* llvm-dwarfdump: Make -brief the default and add a -verbose option instead.Adrian Prantl2017-09-11209-293/+293
| | | | | | Differential Revision: https://reviews.llvm.org/D37717 llvm-svn: 312972
* llvm-dwarfdump: Replace -debug-dump=sect option with individual options.Adrian Prantl2017-09-11223-259/+269
| | | | | | | | | | | | | | | | | | | | | | As discussed on llvm-dev in http://lists.llvm.org/pipermail/llvm-dev/2017-September/117301.html this changes the command line interface of llvm-dwarfdump to match the one used by the dwarfdump utility shipping on macOS. In addition to being shorter to type this format also has the advantage of allowing more than one section to be specified at the same time. In a nutshell, with this change $ llvm-dwarfdump --debug-dump=info $ llvm-dwarfdump --debug-dump=apple-objc becomes $ dwarfdump --debug-info --apple-objc Differential Revision: https://reviews.llvm.org/D37714 llvm-svn: 312970
* [llvm-cov] Allow hiding instantiation/region coverage from summary tablesEli Friedman2017-09-113-6/+3
| | | | | | | | | | | | | Region coverage is difficult to explain without going deep into how coverage is implemented. Instantiation coverage is easier to explain, but probably not useful in most cases (templates don't exist in C, and most C++ code contains relatively few templates). This patch adds the options "-show-region-summary" and "-show-instantiation-summary" to allow hiding those columns. "-show-instantiation-summary" is turned off by default. llvm-svn: 312969
* LowerTypeTests: Add import/export support for targets without absolute ↵Peter Collingbourne2017-09-1112-67/+216
| | | | | | | | | | symbol constants. The rationale is the same as for r312967. Differential Revision: https://reviews.llvm.org/D37408 llvm-svn: 312968
* WholeProgramDevirt: Add import/export support for targets without absolute ↵Peter Collingbourne2017-09-116-16/+47
| | | | | | | | | | | | | | | | | | | symbol constants. Not all targets support the use of absolute symbols to export constants. In particular, ARM has a wide variety of constant encodings that cannot currently be relocated by linkers. So instead of exporting the constants using symbols, export them directly in the summary. The values of the constants are left as zeroes on targets that support symbolic exports. This may result in more cache misses when targeting those architectures as a result of arbitrary changes in constant values, but this seems somewhat unavoidable for now. Differential Revision: https://reviews.llvm.org/D37407 llvm-svn: 312967
* [llvm-cov] Don't attach exec counts to lines which start a skipped regionVedant Kumar2017-09-113-0/+16
| | | | | | | | | These lines by definition don't have an execution count. This is the final part of the fix for: https://bugs.llvm.org/show_bug.cgi?id=34166 llvm-svn: 312955
* [InstSimplify] fix some test names; NFCSanjay Patel2017-09-113-56/+56
| | | | | | Too much division...the quotient is the answer. llvm-svn: 312943
* [InstSimplify] add tests for possible sdiv/srem simplifications; NFCSanjay Patel2017-09-111-0/+354
| | | | | | | | | | As noted in PR34517, the handling of signed div/rem is not on par with unsigned div/rem. Signed is harder to reason about, but it should be possible to handle at least some of these using the same technique that we use for unsigned: use icmp logic to see if there's a relationship between the quotient and divisor. llvm-svn: 312938
* AMDGPU: Allow coldcc callsMatt Arsenault2017-09-111-0/+34
| | | | llvm-svn: 312936
* [mips][microMIPS] add lapc instructionPetar Jovanovic2017-09-1115-17/+54
| | | | | | | | | | Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35984 llvm-svn: 312934
* Unmerge GEPs to reduce register pressure on IndirectBr edges.Hiroshi Yamauchi2017-09-111-0/+60
| | | | | | | | | | | | | | | | | | | | | | | Summary: GEP merging can sometimes increase the number of live values and register pressure across control edges and cause performance problems particularly if the increased register pressure results in spills. This change implements GEP unmerging around an IndirectBr in certain cases to mitigate the issue. This is in the CodeGenPrepare pass (after all the GEP merging has happened.) With this patch, the Python interpreter loop runs faster by ~5%. Reviewers: sanjoy, hfinkel Reviewed By: hfinkel Subscribers: eastig, junbuml, llvm-commits Differential Revision: https://reviews.llvm.org/D36772 llvm-svn: 312930
* [AMDGPU] Produce madak and madmk from the two-address passStanislav Mekhanoshin2017-09-113-3/+113
| | | | | | | | | | These two instructions are normally selected, but when the two address pass converts mac into mad we end up with the mad where we could have one of these. Differential Revision: https://reviews.llvm.org/D37389 llvm-svn: 312928
* X86 Tests: More AVX512 conversions tests. NFCZvi Rackover2017-09-111-0/+885
| | | | | | Adding more tests for AVX512 fp<->int conversions that were missing. llvm-svn: 312921
* [X86][SSE] Add support for X86ISD::PACKSS to ComputeNumSignBitsForTargetNodeSimon Pilgrim2017-09-112-1723/+1719
| | | | | | | | Helps improve combineLogicBlendIntoPBLENDV support by allowing us to peek into through PACKSS truncations of vector comparison results. Differential Revision: https://reviews.llvm.org/D37680 llvm-svn: 312916
* [AMDGPU] exp should not be in WQM modeTim Renouf2017-09-112-14/+58
| | | | | | | | | | | | | | | A mrt exp with vm=1 must be in exact (non-WQM) mode, as it also exports the exec mask as the valid mask to determine which pixels to render. This commit marks any exp as needing to be in exact mode. Actually, if there are multiple mrt exps, only one needs to have vm=1, and only that one needs to be in exact mode. But that is an optimization for another day. Differential Revision: https://reviews.llvm.org/D36305 llvm-svn: 312915
* [X86][SSE] Add further test cases showing failure to compute sign bits ↵Simon Pilgrim2017-09-111-1/+388
| | | | | | | | | through PACKSS Suggested in D37680 Note: had to drop AVX512VL tests as there is an infinite loop in the new tests that needs further investigation (not relevant to D37680). llvm-svn: 312910
* [X86][SKX][KNL] Updating several CodeGen tests to use the attr flag instead ↵Gadi Haber2017-09-113-38/+40
| | | | | | | | | | | | | of mcpu flag NFC. Updated 3 Codegen regression tests to use the -mattr flag instead of the -mcpu flags as follows: Instead of -mcpu=skx use -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq Instead of -mcpu=knl use -mattr=+avx512f Reviewers: delena Revision: https://reviews.llvm.org/D37674 llvm-svn: 312909
* [ARM] Enable the use of SVC anywhere in an IT blockAndre Vieira2017-09-111-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D37374 llvm-svn: 312908
* [Interleved][Stride 3]Adding test for case the VF=64 target with AVX512.Michael Zuckerman2017-09-113-0/+661
| | | | llvm-svn: 312907
* [X86][SSE] Add test showing failure to compute sign bits through PACKSSSimon Pilgrim2017-09-111-0/+65
| | | | | | Prevents combineLogicBlendIntoPBLENDV from merging to PBLENDV llvm-svn: 312906
* [AVR] Enable the '__do_copy_data' functionDylan McKay2017-09-112-0/+10
| | | | | | | | | | | | | Also enables '__do_clear_bss'. These functions are automaticalled called by the CRT if they are declared. We need these to be called otherwise RAM will start completely uninitialised, even though we need to copy RAM variables from progmem to RAM. llvm-svn: 312905
* [GlobalISel][X86] G_ANYEXT support.Igor Breger2017-09-114-0/+604
| | | | | | | | | | | | | | Summary: G_ANYEXT support Reviewers: zvi, delena Reviewed By: delena Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D37675 llvm-svn: 312903
* Fixed a typo in llvm-cov/deferred-region.cpp test.Ilya Biryukov2017-09-111-1/+1
| | | | | | Input redirection was using `2&>1` instead of `2>&1`. llvm-svn: 312902
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-112-15/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515 and also is being recommitted as its first version caused PR34045. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 312898
* Fixed a bug in splitting Scatter operation in the Type Legalizer.Elena Demikhovsky2017-09-111-4/+3
| | | | | | | | | After the split of the Scatter operation, the order of the new instructions is well defined - Lo goes before Hi. Otherwise the semantic of Scatter (from LSB to MSB) is broken. I'm chaining 2 nodes to prevent reordering. Differential Revision https://reviews.llvm.org/D37670 llvm-svn: 312894
* [InstSimplify] refactor udiv/urem code and add tests; NFCISanjay Patel2017-09-102-0/+137
| | | | | | | | | This removes some duplicated code and makes it easier to support signed div/rem in a similar way if we want to do that. Note that the existing comments were not accurate - we don't need a constant divisor to simplify; icmp simplification does more than that. But as the added tests show, it could go even further. llvm-svn: 312885
* Added a test that demonstrates a ug in Scatter scheduling.Elena Demikhovsky2017-09-101-0/+23
| | | | | | | The bug is going to be fixed in an upcomming patch. llvm-svn: 312883
* [X86] Add v2i4 store test case (PR20012)Simon Pilgrim2017-09-091-0/+17
| | | | llvm-svn: 312874
* [X86] Add v2i2 test case (PR20011)Simon Pilgrim2017-09-091-0/+33
| | | | llvm-svn: 312873
* [X86][FMA] Regenerate FMA testsSimon Pilgrim2017-09-094-715/+910
| | | | llvm-svn: 312871
* Merge isKnownNonNull into isKnownNonZeroNuno Lopes2017-09-099-16/+27
| | | | | | | | | It now knows the tricks of both functions. Also, fix a bug that considered allocas of non-zero address space to be always non null Differential Revision: https://reviews.llvm.org/D37628 llvm-svn: 312869
* [X86][SSE] i32 vector multiplications test cases from PR6399Simon Pilgrim2017-09-091-0/+472
| | | | llvm-svn: 312868
* [X86][MOVBE] Fix typo in MOVBE scheduling test namesSimon Pilgrim2017-09-091-21/+21
| | | | | | Copy+paste is not your friend llvm-svn: 312867
* [X86] Don't disable slow INC/DEC if optimizing for sizeCraig Topper2017-09-091-22/+10
| | | | | | | | | | | | | | | | | Summary: Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size. This appears to match gcc behavior. Reviewers: chandlerc, zvi, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37177 llvm-svn: 312866
* [DivRemPairs] split tests per target to account for bots that don't build ↵Sanjay Patel2017-09-095-364/+606
| | | | | | for all targets llvm-svn: 312863
* [DivRempairs] add a pass to optimize div/rem pairs (PR31028)Sanjay Patel2017-09-093-0/+366
| | | | | | | | | | | | | | | | | | This is intended to be a superset of the functionality from D31037 (EarlyCSE) but implemented as an independent pass, so there's no stretching of scope and feature creep for an existing pass. I also proposed a weaker version of this for SimplifyCFG in D30910. And I initially had almost this same functionality as an addition to CGP in the motivating example of PR31028: https://bugs.llvm.org/show_bug.cgi?id=31028 The advantage of positioning this ahead of SimplifyCFG in the pass pipeline is that it can allow more flattening. But it needs to be after passes (InstCombine) that could sink a div/rem and undo the hoisting that is done here. Decomposing remainder may allow removing some code from the backend (PPC and possibly others). Differential Revision: https://reviews.llvm.org/D37121 llvm-svn: 312862
* PPC: Don't select lxv/stxv for insufficiently aligned stack slots.Kyle Butt2017-09-091-0/+46
| | | | | | | | | | | | | | The lxv/stxv instructions require an offset that is 0 % 16. Previously we were selecting lxv/stxv for loads and stores to the stack where the offset from the slot was a multiple of 16, but the stack slot was not 16 or more byte aligned. When the frame gets lowered these transform to r(1|31) + slot + offset. If slot is not aligned, slot + offset may not be 0 % 16. Now we require 16 byte or more alignment for select lxv/stxv to stack slots. Includes a testcase that shows both sufficiently and insufficiently aligned stack slots. llvm-svn: 312843
* bpf: fix test failures due to previous bpf change of assembly code syntaxYonghong Song2017-09-095-6/+6
| | | | | Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 312840
* [TargetTransformInfo] Add a new public interface getInstructionCostGuozhi Wei2017-09-081-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | Current TargetTransformInfo can support throughput cost model and code size model, but sometimes we also need instruction latency cost model in different optimizations. Hal suggested we need a single public interface to query the different cost of an instruction. So I proposed following interface: enum TargetCostKind { TCK_RecipThroughput, ///< Reciprocal throughput. TCK_Latency, ///< The latency of instruction. TCK_CodeSize ///< Instruction code size. }; int getInstructionCost(const Instruction *I, enum TargetCostKind kind) const; All clients should mainly use this function to query the cost of an instruction, parameter <kind> specifies the desired cost model. This patch also provides a simple default implementation of getInstructionLatency. The default getInstructionLatency provides latency numbers for only small number of instruction classes, those latency numbers are only reasonable for modern OOO processors. It can be extended in following ways: Add more detail into this function. Add getXXXLatency function and call it from here. Implement target specific getInstructionLatency function. Differential Revision: https://reviews.llvm.org/D37170 llvm-svn: 312832
* Migrate llvm-symbolizer tests to not use %TDavid Blaikie2017-09-0814-28/+69
| | | | | | (context around the %T removal here: https://reviews.llvm.org/D35396 ) llvm-svn: 312828
* [llvm-cov] Use portable output redirection in a testVedant Kumar2017-09-081-1/+1
| | | | | | A follow-up to a test fix (r312825). llvm-svn: 312826
* [llvm-cov] Try to appease a Windows botVedant Kumar2017-09-081-1/+1
| | | | | | | | | | | | | | | | On a Windows bot, I see a FileCheck error where the source being matched over no longer exists, i.e it seems like it's FileCheck'ing some stale output: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4747 You can see "// CHECK: [[@LINE]]|{{ +}Marker at 19:3 = 1" in the FileCheck stderr, but that CHECK line doesn't exist. Remove the input file to FileCheck before running the test, to try and appease the bot. llvm-svn: 312825
* [llvm-cov] Disable name-compression in a test binaryVedant Kumar2017-09-081-0/+0
| | | | | | | | | | This should fix the lld bot: The Buildbot has detected a new failure on builder llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast while building cfe. Full details are available at: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/16993 llvm-svn: 312821
* AMDGPU: Recompute scc livenessMatt Arsenault2017-09-081-0/+60
| | | | | | | | The various scalar bit operations set SCC, so one is erased or moved it needs to be recomputed. Not sure why the existing tests don't fail on this. llvm-svn: 312819
* [Coverage] Build sorted and unique segmentsVedant Kumar2017-09-082-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | A coverage segment contains a starting line and column, an execution count, and some other metadata. Clients of the coverage library use segments to prepare line-oriented reports. Users of the coverage library depend on segments being unique and sorted in source order. Currently this is not guaranteed (this is why the clang change which introduced deferred regions was reverted). This commit documents the "unique and sorted" condition and asserts that it holds. It also fixes the SegmentBuilder so that it produces correct output in some edge cases. Testing: I've added unit tests for some edge cases. I've also checked that the new SegmentBuilder implementation is fully covered. Apart from running check-profile and the llvm-cov tests, I've successfully used a stage1 llvm-cov to prepare a coverage report for an instrumented clang binary. Differential Revision: https://reviews.llvm.org/D36813 llvm-svn: 312817
* [llvm-cov] Fix a lifetime issueVedant Kumar2017-09-081-0/+4
| | | | | | | This fixes an issue where a std::string was moved to a constructor which accepted a StringRef. llvm-svn: 312816
* [Coverage] Report errors when reading malformed source regionsVedant Kumar2017-09-085-5/+8
| | | | | | | | | | | | | Each source region has a start and end location. Report an error when the end location does not precede the begin location. The old lineExecutionCounts.covmapping test actually had a buggy source region in it. This commit introduces a regenerated copy of the coverage and moves the old copy to malformedRegions.covmapping, for a test. Differential Revision: https://reviews.llvm.org/D37387 llvm-svn: 312814
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