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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2017-09-11 06:18:15 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2017-09-11 06:18:15 +0000 |
| commit | cc477bbceaab693546ee1e8e9ca11e1e3b25e793 (patch) | |
| tree | f7faa6d784f0a0cb7de31f9f96674d938b919e0d /llvm/test | |
| parent | 70a6929f1aa6cb797cd7bb66d54e9f30a2d1ca8f (diff) | |
| download | bcm5719-llvm-cc477bbceaab693546ee1e8e9ca11e1e3b25e793.tar.gz bcm5719-llvm-cc477bbceaab693546ee1e8e9ca11e1e3b25e793.zip | |
Fixed a bug in splitting Scatter operation in the Type Legalizer.
After the split of the Scatter operation, the order of the new instructions is well defined - Lo goes before Hi. Otherwise the semantic of Scatter (from LSB to MSB) is broken.
I'm chaining 2 nodes to prevent reordering.
Differential Revision https://reviews.llvm.org/D37670
llvm-svn: 312894
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/scatter-schedule.ll | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/scatter-schedule.ll b/llvm/test/CodeGen/X86/scatter-schedule.ll index 50c63b388ec..3b26a7c23a8 100644 --- a/llvm/test/CodeGen/X86/scatter-schedule.ll +++ b/llvm/test/CodeGen/X86/scatter-schedule.ll @@ -5,16 +5,15 @@ target triple = "x86_64-unknown-linux-gnu" ; This test checks the order of scatter operations after split. ; The right order is "from LSB to MSB", otherwise the semantic is broken. -; The submitted version of the test demonstrates the bug. define void @test(i64 %x272, <16 x i32*> %x335, <16 x i32> %x270) { ; CHECK-LABEL: test: ; CHECK: # BB#0: -; CHECK-NEXT: vextracti64x4 $1, %zmm2, %ymm3 ; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: kxnorw %k0, %k0, %k2 -; CHECK-NEXT: vpscatterqd %ymm3, (,%zmm1) {%k2} -; CHECK-NEXT: vpscatterqd %ymm2, (,%zmm0) {%k1} +; CHECK-NEXT: vpscatterqd %ymm2, (,%zmm0) {%k2} +; CHECK-NEXT: vextracti64x4 $1, %zmm2, %ymm0 +; CHECK-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1} ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %x270, <16 x i32*> %x335, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>) |
