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* [NVPTX] Re-enable assembly printing support for inline assemblyJustin Holewinski2013-08-241-0/+9
| | | | | | This support was removed by accident during the MC conversion llvm-svn: 189160
* Update test to use rdrnd instead of rdrand.Rafael Espindola2013-08-231-1/+1
| | | | llvm-svn: 189146
* Update tests to use sse4.2 instead of sse42.Rafael Espindola2013-08-2323-24/+24
| | | | llvm-svn: 189145
* Replace more uses of sse41 with sse4.1.Rafael Espindola2013-08-2339-46/+46
| | | | | | | llc using the host cpu features and *waning* on unknown features is probably not a good thing :-( llvm-svn: 189144
* Update a test that I missed in the previous commit.Rafael Espindola2013-08-231-2/+2
| | | | llvm-svn: 189143
* Rename features to match what gcc and clang use.Rafael Espindola2013-08-2312-14/+14
| | | | | | | There is no advantage in being different and using the same names simplifies clang a bit. llvm-svn: 189141
* DataFlowSanitizer: correctly combine labels in the case where they are equal.Peter Collingbourne2013-08-231-4/+5
| | | | llvm-svn: 189133
* [ARM] Fix another ARM FastISel -verify-machineinstrs issue.Joey Gouly2013-08-231-3/+3
| | | | llvm-svn: 189109
* [msan] Fix handling of va_arg overflow area on x86_64.Evgeniy Stepanov2013-08-231-0/+25
| | | | | | | | The code was erroneously reading overflow area shadow from the TLS slot, bypassing the local copy. Reading shadow directly from TLS is wrong, because it can be overwritten by a nested vararg call, if that happens before va_start. llvm-svn: 189104
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-231-0/+46
| | | | llvm-svn: 189103
* Add function attribute 'optnone'.Andrea Di Biagio2013-08-232-2/+22
| | | | | | | | This function attribute indicates that the function is not optimized by any optimization or code generator passes with the exception of interprocedural optimization passes. llvm-svn: 189101
* [SystemZ] Add basic prefetch supportRichard Sandiford2013-08-235-0/+242
| | | | | | Just the instructions and intrinsics for now. llvm-svn: 189100
* [SystemZ] Try reversing comparisons whose first operand is in memoryRichard Sandiford2013-08-2318-2/+430
| | | | | | This allows us to make more use of the many compare reg,mem instructions. llvm-svn: 189099
* [SystemZ] Prefer LHI;ST... over LAY;MV...Richard Sandiford2013-08-236-48/+49
| | | | | | | | | | | | | | | | | | | If we had a store of an integer to memory, and the integer and store size were suitable for a form of MV..., we used MV... no matter what. We could then have sequences like: lay %r2, 0(%r3,%r4) mvi 0(%r2), 4 In these cases it seems better to force the constant into a register and use a normal store: lhi %r2, 4 stc %r2, 0(%r3, %r4) since %r2 is more likely to be hoisted and is easier to rematerialize. llvm-svn: 189098
* Turn MipsOptimizeMathLibCalls into a target-independent scalar transformRichard Sandiford2013-08-232-1/+31
| | | | | | | | | | ...so that it can be used for z too. Most of the code is the same. The only real change is to use TargetTransformInfo to test when a sqrt instruction is available. The pass is opt-in because at the moment it only handles sqrt. llvm-svn: 189097
* ARM: make sure ARM-mode pseudo-inst requires IsARMTim Northover2013-08-231-1/+10
| | | | | | | | | | I'd forgotten that "Requires" blocks override rather than add to the constraints, so my pseudo-instruction was being selected in Thumb mode leading to nonsense instructions. rdar://problem/14817358 llvm-svn: 189096
* [PR11606] ocaml bindings tests produce binaries in source dirDaniel Dunbar2013-08-239-9/+36
| | | | | | | | | | - Workaround for ocamlopt producing outputs adjacent to its source inputs, by having the tests copy the inputs into temporary directories in the output paths before building. - Patch by edward-san. llvm-svn: 189081
* Filecheckize some tests.Michael Gottesman2013-08-232-3/+10
| | | | llvm-svn: 189079
* Update StripDeadDebugInfo to use DebugInfoFinder so that it is no longer ↵Michael Gottesman2013-08-233-53/+59
| | | | | | | | | | | | | | | | | | | | | stale to the point of not working and more resilient to debug info changes. The current version of StripDeadDebugInfo became stale and no longer actually worked since it was expecting an older version of debug info. This patch updates it to use DebugInfoFinder and the modern DebugInfo classes as much as possible to make it more redundent to such changes. Additionally, the only place where that was avoided (the code where we replace the old sets with the new), I call verify on the DIContextUnit implying that if the format changes and my live set changes no longer make sense an assert will be hit. In order to ensure that that occurs I have included a test case. The actual stripping of the dead debug info follows the same strategy as was used before in this class: find the live set and replace the old set in the given compile unit (which may contain dead global variables/functions) with the new live one. llvm-svn: 189078
* [stack protector] Work around an issue with the BMOVPCB_CALL instruction on ↵Michael Gottesman2013-08-221-0/+32
| | | | | | | | | | ARM by disabling does not return on __stack_chk_fail. This is to fix the bots while I look to see if there is something I can do here. rdar://14811848 llvm-svn: 189076
* Update to remove the no-frame-pointer-elim-non-leaf flag if it was set to ↵Bill Wendling2013-08-2246-74/+74
| | | | | | 'false'. llvm-svn: 189068
* Fix some tests. The 'false' version just omits the attribute altogether.Bill Wendling2013-08-222-5/+5
| | | | llvm-svn: 189065
* FileCheckize some tests.Bill Wendling2013-08-2215-25/+162
| | | | llvm-svn: 189060
* R600/SI: Fix another case of illegal VGPR to SGPR copyTom Stellard2013-08-221-3/+142
| | | | | | | | This fixes a crash in Unigine Tropics. https://bugs.freedesktop.org/show_bug.cgi?id=68389 llvm-svn: 189057
* DataFlowSanitizer: Replace non-instrumented aliases of instrumented ↵Peter Collingbourne2013-08-222-3/+16
| | | | | | | | functions, and vice versa, with wrappers. Differential Revision: http://llvm-reviews.chandlerc.com/D1442 llvm-svn: 189054
* DataFlowSanitizer: Prefix the name of each instrumented function with "dfs$".Peter Collingbourne2013-08-229-22/+36
| | | | | | | | | | | | | | | | DFSan changes the ABI of each function in the module. This makes it possible for a function with the native ABI to be called with the instrumented ABI, or vice versa, thus possibly invoking undefined behavior. A simple way of statically detecting instances of this problem is to prepend the prefix "dfs$" to the name of each instrumented-ABI function. This will not catch every such problem; in particular function pointers passed across the instrumented-native barrier cannot be used on the other side. These problems could potentially be caught dynamically. Differential Revision: http://llvm-reviews.chandlerc.com/D1373 llvm-svn: 189052
* [Debug Info Tests] Update testing cases.Manman Ren2013-08-227-23/+22
| | | | | | | | | A single metadata will not span multiple lines. This also helps me with my script to automatic update the testing cases. A debug info testing case should have a llvm.dbg.cu. Do not use hard-coded id for debug nodes. llvm-svn: 189033
* [ARMv8] Add CodeGen support for VSEL.Joey Gouly2013-08-221-0/+309
| | | | | | | | This uses the ARMcmov pattern that Tim cleaned up in r188995. Thanks to Simon Tatham for his floating point help! llvm-svn: 189024
* Fix ARM vcvt encoding when the number of fractional bits is zero.Mihai Popa2013-08-221-0/+16
| | | | | | | | | | | The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
* Teach the SLP vectorizer the correct way to check for consecutive accessChandler Carruth2013-08-221-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | using GEPs. Previously, it used a number of different heuristics for analyzing the GEPs. Several of these were conservatively correct, but failed to fall back to SCEV even when SCEV might have given a reasonable answer. One was simply incorrect in how it was formulated. There was good code already to recursively evaluate the constant offsets in GEPs, look through pointer casts, etc. I gathered this into a form code like the SLP code can use in a previous commit, which allows all of this code to become quite simple. There is some performance (compile time) concern here at first glance as we're directly attempting to walk both pointers constant GEP chains. However, a couple of thoughts: 1) The very common cases where there is a dynamic pointer, and a second pointer at a constant offset (usually a stride) from it, this code will actually not do any unnecessary work. 2) InstCombine and other passes work very hard to collapse constant GEPs, so it will be rare that we iterate here for a long time. That said, if there remain performance problems here, there are some obvious things that can improve the situation immensely. Doing a vectorizer-pass-wide memoizer for each individual layer of pointer values, their base values, and the constant offset is likely to be able to completely remove redundant work and strictly limit the scaling of the work to scrape these GEPs. Since this optimization was not done on the prior version (which would still benefit from it), I've not done it here. But if folks have benchmarks that slow down it should be straight forward for them to add. I've added a test case, but I'm not really confident of the amount of testing done for different access patterns, strides, and pointer manipulation. llvm-svn: 189007
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-222-2/+2
| | | | | | we pass these tests with -verify-machineinstrs. llvm-svn: 189006
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-0/+23
| | | | | | | The function call to external function should come with PLT relocation type if the PIC relocation model is used. llvm-svn: 189002
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-224-10/+18
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* ARM: respect tied 64-bit inlineasm operands when printingTim Northover2013-08-221-0/+10
| | | | | | | The code for 'Q' and 'R' operand modifiers needs to look through tied operands to discover the register class. llvm-svn: 188990
* [stackprotector] When finding the split point to splice off the end of a ↵Michael Gottesman2013-08-221-0/+99
| | | | | | | | parentmbb into a successmbb, include any DBG_VALUE MI. Fix for PR16954. llvm-svn: 188987
* Teach LoopVectorize about address space sizesMatt Arsenault2013-08-221-2/+29
| | | | llvm-svn: 188980
* FileCheck-ize tests.Bill Wendling2013-08-2226-35/+98
| | | | llvm-svn: 188971
* ARM: R9 is not safe to use for tcGPR.Jim Grosbach2013-08-221-0/+14
| | | | | | | | | Indirect tail-calls shouldn't use R9 for the branch destination, as it's not reliably a call-clobbered register. rdar://14793425 llvm-svn: 188967
* SelectionDAG: Make sure stores are always added to the LegalizedNodes listTom Stellard2013-08-211-0/+20
| | | | | | | | | | | | | | | | When truncated vector stores were being custom lowered in VectorLegalizer::LegalizeOp(), the old (illegal) and new (legal) node pair was not being added to LegalizedNodes list. Instead of the legalized result being passed to VectorLegalizer::TranslateLegalizeResult(), the result was being passed back into VectorLegalizer::LegalizeOp(), which ended up adding a (new, new) pair to the list instead. This was causing an assertion failure when a custom lowered truncated vector store was the last instruction a basic block and the VectorLegalizer was unable to find it in the LegalizedNodes list when updating the DAG root. llvm-svn: 188953
* [tests] Update fma3 check to work with Py3.Daniel Dunbar2013-08-211-1/+2
| | | | llvm-svn: 188950
* TBAA: remove !tbaa from testing cases when they are not needed.Manman Ren2013-08-2116-674/+584
| | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. llvm-svn: 188944
* Teach BaseIndexOffset::match to identify base pointers in loops.Juergen Ributzka2013-08-211-0/+30
| | | | | | | | | | | | | | The small utility function that pattern matches Base + Index + Offset patterns for loads and stores fails to recognize the base pointer for loads/stores from/into an array at offset 0 inside a loop. As a result DAGCombiner::MergeConsecutiveStores was not able to merge all stores. This commit fixes the issue by adding an additional pattern match and also a test case. Reviewer: Nadav llvm-svn: 188936
* Teach InstCombine about address spacesMatt Arsenault2013-08-215-70/+406
| | | | llvm-svn: 188926
* MC CFG: Remap enough for data too, analoguous to r188873.Ahmed Bougacha2013-08-211-0/+48
| | | | llvm-svn: 188925
* Add testcase for r188873: MCTextAtom boundaries.Ahmed Bougacha2013-08-211-0/+39
| | | | | | | Check that they are correctly computed if the last instruction is larger than 1 byte. llvm-svn: 188923
* Add test for bitcast array ptrs with address spacesMatt Arsenault2013-08-211-0/+22
| | | | llvm-svn: 188919
* Add enforce known alignment test with address spaceMatt Arsenault2013-08-211-3/+23
| | | | llvm-svn: 188917
* A minor change for an obvous problem caused by r188451:Hao Liu2013-08-211-2/+2
| | | | | | | def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 63;}]>{ As it seems Imm <63 should be Imm <= 63. ImmLeaf is used in pattern match, but there is already a function check the shift amount range, so just remove ImmLeaf. Also add a test to check 63. llvm-svn: 188911
* Add -mcpu to two X86 tests.Joey Gouly2013-08-212-2/+2
| | | | | | These tests are failing on Haswell CPUs due to different instruction selection. llvm-svn: 188908
* Add basic YAML MC CFG testcase.Ahmed Bougacha2013-08-211-0/+86
| | | | | | Drive-by llvm-objdump cleanup (don't hardcode ToolName). llvm-svn: 188904
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