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* Revert r188449 as it turns out we're just missing the instructions that need ↵Craig Topper2013-08-151-8/+0
| | | | | | the v16i32/v16f32 matching. llvm-svn: 188454
* Clang and AArch64 backend patches to support shll/shl and vmovl instructions ↵Hao Liu2013-08-156-0/+402
| | | | | | and ACLE functions llvm-svn: 188451
* Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that ↵Craig Topper2013-08-151-0/+8
| | | | | | type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask. llvm-svn: 188449
* R600/SI: Improve legalization of vector operationsTom Stellard2013-08-141-0/+111
| | | | | | This should fix hangs in the OpenCL piglit tests. llvm-svn: 188431
* R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsicsTom Stellard2013-08-141-0/+17
| | | | llvm-svn: 188430
* R600/SI: Convert v16i8 resource descriptors to i128Tom Stellard2013-08-142-34/+34
| | | | | | | | | | | | | Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 llvm-svn: 188429
* R600/SI: Use i8 types for resource descriptors in testsTom Stellard2013-08-144-62/+62
| | | | | | | We switched from i32 to i8 types a while ago and the tests were never updated. llvm-svn: 188428
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-142-1/+51
| | | | | | | | | | | | Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. llvm-svn: 188427
* R600/SI: Assign a register class to the $vaddr operand for MIMG instructionsTom Stellard2013-08-141-0/+44
| | | | | | | The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. llvm-svn: 188425
* DataFlowSanitizer: move abilist input file to Inputs.Peter Collingbourne2013-08-142-1/+1
| | | | llvm-svn: 188423
* R600/SI: Handle MSAA texture targetsTom Stellard2013-08-141-1/+1
| | | | | | | Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> llvm-svn: 188421
* R600/SI: Allow conversion between v32i8 and v8i32Tom Stellard2013-08-141-0/+21
| | | | | | | Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> llvm-svn: 188420
* R600/SI: Add pattern for fp_to_uintTom Stellard2013-08-141-9/+18
| | | | | | | | | This fixes the F2U opcode for the Mesa driver. Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> llvm-svn: 188418
* DataFlowSanitizer: Instrumentation for memset.Peter Collingbourne2013-08-141-0/+11
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D1395 llvm-svn: 188412
* Actually fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-141-0/+43
| | | | | | | | | | This is a follow-up to r187693, correcting that code to request the correct register class. The previous version, with the wrong register class, was not really correcting the constraints, but rather was removing them. Coincidentally, this fixed the failing test case in r187693, but obviously created other problems. llvm-svn: 188407
* DataFlowSanitizer: greylist is now ABI list.Peter Collingbourne2013-08-142-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces the old incomplete greylist functionality with an ABI list, which can provide more detailed information about the ABI and semantics of specific functions. The pass treats every function in the "uninstrumented" category in the ABI list file as conforming to the "native" (i.e. unsanitized) ABI. Unless the ABI list contains additional categories for those functions, a call to one of those functions will produce a warning message, as the labelling behaviour of the function is unknown. The other supported categories are "functional", "discard" and "custom". - "discard" -- This function does not write to (user-accessible) memory, and its return value is unlabelled. - "functional" -- This function does not write to (user-accessible) memory, and the label of its return value is the union of the label of its arguments. - "custom" -- Instead of calling the function, a custom wrapper __dfsw_F is called, where F is the name of the function. This function may wrap the original function or provide its own implementation. Differential Revision: http://llvm-reviews.chandlerc.com/D1345 llvm-svn: 188402
* llvm-symbolizer: add support for .gnu_debuglink sectionAlexey Samsonov2013-08-142-0/+4
| | | | llvm-svn: 188386
* Let t2LDRBi8 and t2LDRBi12 have same Base PointerRenato Golin2013-08-141-0/+64
| | | | | | | | | | | | | | When determining if two different loads are from the same base address, this patch allows one load to use a t2LDRi8 address mode and another to use a t2LDRi12 address mode. The current implementation is very conservative and this allows the case of differing Thumb2 byte loads to be considered. Allowing these differing modes instead of forcing the exact same opcode is useful for situations where one opcodes loads from a base address+1 and a second opcode loads for a base address-1. Patch by Daniel Stewart. llvm-svn: 188385
* Add test-case for hex floating-literalsTim Northover2013-08-141-0/+3
| | | | | | Somehow I forgot to test one of the error conditions I'd added. llvm-svn: 188372
* Support C99 hexadecimal floating-point literals in assemblyTim Northover2013-08-141-1/+36
| | | | | | | | It's useful to be able to write down floating-point numbers without having to worry about what they'll be rounded to (as C99 discovered), this extends that ability to the MC assembly parsers. llvm-svn: 188370
* [mips] Fix bug in parsing accumulator registers.Akira Hatanaka2013-08-141-0/+14
| | | | llvm-svn: 188344
* llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32.NAKAMURA Takumi2013-08-141-2/+2
| | | | llvm-svn: 188340
* Fix always creating GEP with i32 indicesMatt Arsenault2013-08-141-3/+22
| | | | | | | | | | | | | | | | Use the pointer size if datalayout is available. Use i64 if it's not, which is consistent with what other places do when the pointer size is unknown. The test doesn't really test this in a useful way since it will be transformed to that later anyway, but this now tests it for non-zero arrays and when datalayout isn't available. The cases in visitGetElementPtrInst should save an extra re-visit to the newly created GEP since it won't need to cleanup after itself. llvm-svn: 188339
* [mips] Properly parse registers that appear in inline-asm constraints.Akira Hatanaka2013-08-141-0/+18
| | | | llvm-svn: 188336
* BBVectorize: Add initial stores to the write set when tracking usesHal Finkel2013-08-131-0/+144
| | | | | | | | | | | | | | | | When computing the use set of a store, we need to add the store to the write set prior to iterating over later instructions. Otherwise, if there is a later aliasing load of that store, that load will not be tagged as a use, and bad things will happen. trackUsesOfI still adds later dependent stores of an instruction to that instruction's write set, but it never sees the original instruction, and so when tracking uses of a store, the store must be added to the write set by the caller. Fixes PR16834. llvm-svn: 188329
* Remove duplicate copy of testcase in r188327.Nick Lewycky2013-08-131-26/+0
| | | | llvm-svn: 188328
* Revert r187191, which broke opt -mem2reg on the testcases included in PR16867.Nick Lewycky2013-08-132-70/+52
| | | | | | | | | | | | However, opt -O2 doesn't run mem2reg directly so nobody noticed until r188146 when SROA started sending more things directly down the PromoteMemToReg path. In order to revert r187191, I also revert dependent revisions r187296, r187322 and r188146. Fixes PR16867. Does not add the testcases from that PR, but both of them should get added for both mem2reg and sroa when this revert gets unreverted. llvm-svn: 188327
* DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)Jim Grosbach2013-08-132-0/+27
| | | | | | | | | | | | | | | | | | | | | | | A common idiom is to use zero and all-ones as sentinal values and to check for both in a single conditional ("x != 0 && x != (unsigned)-1"). That generates code, for i32, like: testl %edi, %edi setne %al cmpl $-1, %edi setne %cl andb %al, %cl With this transform, we generate the simpler: incl %edi cmpl $1, %edi seta %al Similar improvements for other integer sizes and on other platforms. In general, combining the two setcc instructions into one is better. rdar://14689217 llvm-svn: 188315
* [Mips] Support for unaligned load/store microMips instructionsJack Carter2013-08-131-0/+26
| | | | | | | | This includes instructions lwl, lwr, swl and swr. Patch by Zoran Jovnovic llvm-svn: 188312
* Output DW_AT_stmt_list dwarf debug info as DW_FORM_sec_offset instead of ↵Carlo Kok2013-08-131-0/+40
| | | | | | DW_FORM_data4 as it is a section offset (fixes the coff/dwarf debug info statement locations) llvm-svn: 188297
* ARMv8: SWP and SWPB are obsoleted on ARMv8.Joey Gouly2013-08-131-0/+7
| | | | llvm-svn: 188288
* Fix signed overflow in when computing encodings for ADR instructionsMihai Popa2013-08-131-1/+2
| | | | llvm-svn: 188268
* AVX-512: Added CMP and BLEND instructions.Elena Demikhovsky2013-08-131-0/+113
| | | | | | Lowering for SETCC. llvm-svn: 188265
* Pass DIEHash::collectAttributes output argument by-pointer instead of by-value.Evgeniy Stepanov2013-08-131-2/+2
| | | | | | Before this, collectAttributes() was operating on a local object. llvm-svn: 188254
* [-cxx-abi microsoft] Stick zero initialized symbols into the .bss section ↵David Majnemer2013-08-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | for COFF Summary: We need to do two things: - Initialize BSSSection in MCObjectFileInfo::InitCOFFMCObjectFileInfo - Teach TargetLoweringObjectFileCOFF::SelectSectionForGlobal what to do with it This fixes PR16861. Reviewers: rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1361 llvm-svn: 188244
* Add the start of DIE hashing for DWARF4 type units and split dwarfEric Christopher2013-08-131-0/+15
| | | | | | | | | | CUs. Currently only hashes the name of CUs and the names of any children, but it's an obvious first step to show the framework. The testcase should continue to be correct, however, as it's an empty TU. llvm-svn: 188243
* Add comment and source to testcase.Eric Christopher2013-08-121-0/+10
| | | | llvm-svn: 188234
* [FileCheck] Fix a bug that cause FileCheck to misidentify check-prefixRui Ueyama2013-08-122-0/+16
| | | | | | | | | FileCheck should check to make sure the prefix was found, and not a word containing it (e.g -check-prefix=BASEREL shouldn't match NOBASEREL). Patch by Ron Ofir. llvm-svn: 188221
* Fix a crash with X86 Mach-O and a subtraction expression where both symbols areKevin Enderby2013-08-121-0/+5
| | | | | | | | | undefined and produce an error message instead as this is a non-relocatable expression with X86 Mach-O. rdar://8920876 llvm-svn: 188218
* Reapply r188119 now that the bug it exposed is fixed.Peter Collingbourne2013-08-121-2/+12
| | | | llvm-svn: 188217
* R600: Set scheduling preference to Sched::SourceTom Stellard2013-08-128-8/+8
| | | | | | | | | | | | | | | | | | | | | | | R600 doesn't need to do any scheduling on the SelectionDAG now that it has a very good MachineScheduler. Also, using the VLIW SelectionDAG scheduler was having a major impact on compile times. For example with the phatk kernel here are the LLVM IR to machine code compile times: With Sched::VLIW Total Compile Time: 1.4890 Seconds (User + System) SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System) With Sched::Source Total Compile Time: 0.3330 Seconds (User + System) SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System) The code ouput was identical with both schedulers. This may not be true for all programs, but it gives me confidence that there won't be much reduction, if any, in code quality by using Sched::Source. llvm-svn: 188215
* Move the addition of the dwo_id as late as possible after everythingEric Christopher2013-08-121-2/+2
| | | | | | has been finalized except for sizes and offsets. Update test accordingly. llvm-svn: 188199
* Fix PR16797 - Support PHINodes with multiple inputs from the same basic block.Nadav Rotem2013-08-121-0/+41
| | | | | | | Do not generate new vector values for the same entries because we know that the incoming values from the same block must be identical. llvm-svn: 188185
* This patch implements ei and di instructions for mips. Test cases are added.Vladimir Medic2013-08-121-1/+19
| | | | llvm-svn: 188176
* Fix FileCheck --check-prefix lines.Tim Northover2013-08-1216-41/+41
| | | | | | | | | | Various tests had sprung up over the years which had --check-prefix=ABC on the RUN line, but "CHECK-ABC:" later on. This happened to work before, but was strictly incorrect. FileCheck is getting stricter soon though. Patch by Ron Ofir. llvm-svn: 188173
* [SystemZ] Use CLC and IPM to implement memcmpRichard Sandiford2013-08-121-0/+134
| | | | | | | For now this is restricted to fixed-length comparisons with a length in the range [1, 256], as for memcpy() and MVC. llvm-svn: 188163
* [SystemZ] Add a definition of the CLC instructionRichard Sandiford2013-08-123-0/+142
| | | | llvm-svn: 188162
* [SystemZ] Add a definition of the IPM instructionRichard Sandiford2013-08-122-0/+17
| | | | llvm-svn: 188161
* Allow compatible extension attributes for tail callsTim Northover2013-08-122-3/+59
| | | | | | | | If the tail-callee and caller give the same bits via the same signext/zeroext attribute then a tail-call should be allowed, since the extension has already been done by the callee. llvm-svn: 188159
* Fix big-endian handling of integer-to-vector bitcasts in InstCombineRichard Sandiford2013-08-121-0/+41
| | | | | | | | | | These functions used to assume that the lsb of an integer corresponds to vector element 0, whereas for big-endian it's the other way around: the msb is in the first element and the lsb is in the last element. Fixes MultiSource/Benchmarks/mediabench/gsm/toast for z. llvm-svn: 188155
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