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* Optimize store of "bitcast" from vector to aggregate.Arch D. Robison2016-04-251-0/+74
| | | | | | | | | | | This patch is what was the "instcombine" portion of D14185, with an additional test added (see julia_pseudovec in test/Transforms/InstCombine/insert-val-extract-elem.ll). The patch causes instcombine to replace sequences of extractelement-insertvalue-store that act essentially like a bitcast followed by a store. Differential review: http://reviews.llvm.org/D14260 llvm-svn: 267482
* ARM: put extern __thread stubs in a special section.Tim Northover2016-04-252-0/+63
| | | | | | | The linker needs to know that the symbols are thread-local to do its job properly. llvm-svn: 267473
* Re-apply r267206 with a fix for the encoding problem: when the immediate ofQuentin Colombet2016-04-251-5/+52
| | | | | | | | | | | | | | | | | | log2(Mask) is smaller than 32, we must use the 32-bit variant because the 64-bit variant cannot encode it. Therefore, set the subreg part accordingly. [AArch64] Fix optimizeCondBranch logic. The opcode for the optimized branch does not depend on the size of the activate bits in the AND masks, but the AND opcode itself. Indeed, we need to use a X or W variant based on the AND variant not based on whether the mask fits into the related variant. Otherwise, we may end up using the W variant of the optimized branch for 64-bit register inputs! This fixes the last make check verifier issues for AArch64: PR27479. llvm-svn: 267465
* AMDGPU: Implement addrspacecastMatt Arsenault2016-04-253-22/+274
| | | | llvm-svn: 267452
* AMDGPU: Add queue ptr intrinsicMatt Arsenault2016-04-252-0/+30
| | | | llvm-svn: 267451
* [gold] Fix linkInModule and extend common.ll test.Evgeniy Stepanov2016-04-254-9/+29
| | | | | | | | | | Fix early exit from linkInModule. IRMover::move returns false on success and true on error. Add a few more cases of merged common linkage variables with different sizes and alignments. llvm-svn: 267437
* Fix typo from r267432.Chad Rosier2016-04-251-2/+2
| | | | llvm-svn: 267436
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-0/+9
| | | | | | Remember to svn add the new file. llvm-svn: 267435
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-9/+0
| | | | llvm-svn: 267434
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-251-0/+72
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
* [ValueTracking] Add an additional test case for r266767 where one operand is ↵Chad Rosier2016-04-251-0/+24
| | | | | | a const. llvm-svn: 267432
* Resubmit "Refactor raw pdb dumper into library"Zachary Turner2016-04-251-1/+1
| | | | | | | This fixes a number of endianness issues as well as an ODR violation that hopefully causes everything to be happy. llvm-svn: 267431
* [ValueTracking] Improve isImpliedCondition when the dominating cond is false.Chad Rosier2016-04-252-0/+389
| | | | llvm-svn: 267430
* dsymutil: Only warn about clang module DWO id mismatches in verbose mode.Adrian Prantl2016-04-251-1/+1
| | | | | | | | | | Until PR27449 (https://llvm.org/bugs/show_bug.cgi?id=27449) is fixed in clang this warning is pointless, since ASTFileSignatures will change randomly when a module is rebuilt. rdar://problem/25610919 llvm-svn: 267427
* add tests for potential CGP transform (PR27344)Sanjay Patel2016-04-251-0/+32
| | | | llvm-svn: 267426
* [PR27390] [CodeGen] Reject indexed loads in CombinerDAG.Marcin Koscielnicki2016-04-251-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | visitAND, when folding and (load) forgets to check which output of an indexed load is involved, happily folding the updated address output on the following testcase: target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" %typ = type { i32, i32 } define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) { %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1 %1 = load i32, i32* %b, align 4 %2 = ptrtoint i32* %b to i64 %3 = and i64 %2, -35184372088833 %4 = inttoptr i64 %3 to i32* %_msld = load i32, i32* %4, align 4 %zzz = add i32 %1, %_msld ret i32 %zzz } Fix this by checking ResNo. I've found a few more places that currently neglect to check for indexed load, and tightened them up as well, but I don't have test cases for them. In fact, they might not be triggerable at all, at least with current targets. Still, better safe than sorry. Differential Revision: http://reviews.llvm.org/D19202 llvm-svn: 267420
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-256-18/+2
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-2512-111/+0
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [x86] auto-generate checks for cmov testsSanjay Patel2016-04-251-14/+32
| | | | llvm-svn: 267417
* [WinEH] Update SplitAnalysis::computeLastSplitPoint to cope with multiple EH ↵David Majnemer2016-04-251-0/+67
| | | | | | | | | | | | | | | | | | | successors We didn't have logic to correctly handle CFGs where there was more than one EH-pad successor (these are novel with WinEH). There were situations where a register was live in one exceptional successor but not another but the code as written would only consider the first exceptional successor it found. This resulted in split points which were insufficiently early if an invoke was present. This fixes PR27501. N.B. This removes getLandingPadSuccessor. llvm-svn: 267412
* [ARM] Add support for the X asm constraintSilviu Baranga2016-04-252-0/+178
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for the X asm constraint. To do this, we lower the constraint to either a "w" or "r" constraint depending on the operand type (both constraints are supported on ARM). Fixes PR26493 Reviewers: t.p.northover, echristo, rengolin Subscribers: joker.eph, jgreenhalgh, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19061 llvm-svn: 267411
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-254-12/+56
| | | | | | | | | | | | | Added hwreg(reg[,offset,width]) syntax. Default offset = 0, default width = 32. Possibility to specify 16-bit immediate kept. Added out-of-range checks. Disassembling is always to hwreg(...) format. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19329 llvm-svn: 267410
* [Hexagon] Correctly set "Flags" in ELF headerKrzysztof Parzyszek2016-04-251-0/+9
| | | | llvm-svn: 267397
* [GlobalOpt] Allow constant globals to be SRA'dJames Molloy2016-04-251-0/+21
| | | | | | | | The current logic assumes that any constant global will never be SRA'd. I presume this is because normally constant globals can be pushed into their uses and deleted. However, that sometimes can't happen (which is where you really want SRA, so the elements that can be eliminated, are!). There seems to be no reason why we can't SRA constants too, so let's do it. llvm-svn: 267393
* [Coverage] Restore the correct count value after processing a nested region ↵Igor Kudrin2016-04-251-2/+2
| | | | | | | | | | | | | in case of combined regions. If several regions cover the same area of code, we have to restore the combined value for that area when return from a nested region. This patch achieves that by combining regions before calling buildSegments. Differential Revision: http://reviews.llvm.org/D18610 llvm-svn: 267390
* [SCEV] Improve the run-time checking of the NoWrap predicateSilviu Baranga2016-04-251-12/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This implements a new method of run-time checking the NoWrap SCEV predicates, which should be easier to optimize and nicer for targets that don't correctly handle multiplication/addition of large integer types (like i128). If the AddRec is {a,+,b} and the backedge taken count is c, the idea is to check that |b| * c doesn't have unsigned overflow, and depending on the sign of b, that: a + |b| * c >= a (b >= 0) or a - |b| * c <= a (b <= 0) where the comparisons above are signed or unsigned, depending on the flag that we're checking. The advantage of doing this is that we avoid extending to a larger type and we avoid the multiplication of large types (multiplying i128 can be expensive). Reviewers: sanjoy Subscribers: llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D19266 llvm-svn: 267389
* [PowerPC] [PR27387] Disallow r0 for ADD8TLS.Marcin Koscielnicki2016-04-251-0/+43
| | | | | | | | | | | ADD8TLS, a variant of add instruction used for initial-exec TLS, currently accepts r0 as a source register. While add itself supports r0 just fine, linker can relax it to a local-exec sequence, converting it to addi - which doesn't support r0. Differential Revision: http://reviews.llvm.org/D19193 llvm-svn: 267388
* Fixing wrong mask size error. From __mmask8 to __mmask16.Michael Zuckerman2016-04-251-5/+5
| | | | | | | Was reviewed over the shoulder by AsafBadouh. Connected to review http://reviews.llvm.org/D19195. llvm-svn: 267379
* [X86] Add a complete set of tests for all operand sizes of cttz/ctlz with ↵Craig Topper2016-04-251-6/+123
| | | | | | and without zero undef being lowered to bsf/bsr. llvm-svn: 267373
* Verifier: Verify that each inlinable callsite of a debug-info-bearing functionAdrian Prantl2016-04-243-2/+66
| | | | | | | | | | | | | in a debug-info-bearing function has a debug location attached to it. Failure to do so causes an "!dbg attachment points at wrong subprogram for function" assertion failure when the inliner sets up inline scope info. rdar://problem/25878916 This reaplies r267320 without changes after fixing an issue in the OpenMP IR generator in clang. llvm-svn: 267370
* Also check the IR.Rafael Espindola2016-04-241-0/+4
| | | | llvm-svn: 267367
* Add a test for how we handle protected visibility.Rafael Espindola2016-04-242-0/+22
| | | | llvm-svn: 267366
* [X86][AVX] Added PR24935 test caseSimon Pilgrim2016-04-241-0/+39
| | | | llvm-svn: 267362
* ARM: fix __chkstk Frame Setup on WoASaleem Abdulrasool2016-04-244-9/+9
| | | | | | | | | | | | This corrects the MI annotations for the stack adjustment following the __chkstk invocation. We were marking the original SP usage as a Def rather than Kill. The (new) assigned value is the definition, the original reference is killed. Adjust the ISelLowering to mark Kills and FrameSetup as well. This partially resolves PR27480. llvm-svn: 267361
* [InstCombine][SSE] Reduce DIVSS/DIVSD to FDIV if only first element is requiredSimon Pilgrim2016-04-242-10/+4
| | | | | | As discussed on D19318, if we only demand the first element of a DIVSS/DIVSD intrinsic, then reduce to a FDIV call. This matches the existing FADD/FSUB/FMUL patterns. llvm-svn: 267359
* [InstCombine][SSE] Demanded vector elements for scalar intrinsics (Part 2 of 2)Simon Pilgrim2016-04-244-182/+60
| | | | | | | | | | | | | | | | Split from D17490. This patch improves support for determining the demanded vector elements through SSE scalar intrinsics: 1 - demanded vector element support for unary and some extra binary scalar intrinsics (RCP/RSQRT/SQRT/FRCZ and ADD/CMP/DIV/ROUND). 2 - addss/addsd get simplified to a fadd call if we aren't interested in the pass through elements 3 - if we don't need the lowest element of a scalar operation then just use the first argument (the pass through elements) directly We can add support for propagating demanded elements through any equivalent packed SSE intrinsics in a future patch (these wouldn't use the pass through patterns). Differential Revision: http://reviews.llvm.org/D19318 llvm-svn: 267357
* [InstCombine][SSE] Demanded vector elements for scalar intrinsics (Part 1 of 2)Simon Pilgrim2016-04-243-145/+74
| | | | | | | | | | | | This patch improves support for determining the demanded vector elements through SSE scalar intrinsics: 1 - recognise that we only need the lowest element of the second input for binary scalar operations (and all the elements of the first input) 2 - recognise that the roundss/roundsd intrinsics use the lowest element of the second input and the remaining elements from the first input Differential Revision: http://reviews.llvm.org/D17490 llvm-svn: 267356
* [X86][SSE] Added SSSE3/AVX/AVX2 BITREVERSE testsSimon Pilgrim2016-04-241-52/+14603
| | | | | | Codegen is pretty bad at the moment but could use PSHUFB quite efficiently llvm-svn: 267347
* [X86][XOP] Fixed VPPERM permute op decoding (PR27472).Simon Pilgrim2016-04-241-1/+1
| | | | | | Fixed issue with VPPERM target shuffle mask decoding that was incorrectly masking off the 3-bit permute op with a 2-bit mask. llvm-svn: 267346
* [X86][SSE] Improved support for decoding target shuffle masks through bitcastsSimon Pilgrim2016-04-242-13/+3
| | | | | | | | Reused the ability to split constants of a type wider than the shuffle mask to work with masks generated from scalar constants transfered to xmm. This fixes an issue preventing PSHUFB target shuffle masks decoding rematerialized scalar constants and also exposes the XOP VPPERM bug described in PR27472. llvm-svn: 267343
* [SystemZ] [SSP] Add support for LOAD_STACK_GUARD.Marcin Koscielnicki2016-04-241-0/+35
| | | | | | | | | | | | | | This fixes PR22248 on s390x. The previous attempt at this was D19101, which was before LOAD_STACK_GUARD existed. Compared to the previous version, this always emits a rather ugly block of 4 instructions, involving a thread pointer load that can't be shared with other potential users. However, this is necessary for SSP - spilling the guard value (or thread pointer used to load it) is counter to the goal, since it could be overwritten along with the frame it protects. Differential Revision: http://reviews.llvm.org/D19363 llvm-svn: 267340
* [X86][SSE] Demonstrate issue with decoding shuffle masks that have been ↵Simon Pilgrim2016-04-242-0/+37
| | | | | | | | lowered as rematerialized constants on scalar unit Found whilst investigating PR27472 llvm-svn: 267339
* llvm/test/tools/gold/X86/thinlto.ll: Possible fix corresponding to r267318.NAKAMURA Takumi2016-04-241-0/+1
| | | | llvm-svn: 267334
* BitcodeReader: Fix some holes in upgrade from r267296Duncan P. N. Exon Smith2016-04-242-1/+9
| | | | | | | | | | | | | | Add tests for some missing cases to bitcode upgrade in r267296. - DICompositeType with an 'elements:' field, which will cause it to be involved in a cycle after the upgrade. - A DIDerivedType that references a class in 'extraData:'. I updated test/Bitcode/dityperefs-3.8.ll with the missing cases and regenerated test/Bitcode/dityperefs-3.8.ll.bc. llvm-svn: 267332
* Add "hasSection" flag in the SummaryMehdi Amini2016-04-241-0/+11
| | | | | | | | | | | Reviewers: tejohnson Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19405 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267329
* [MachineCombiner] Support for floating-point FMA on ARM64 (re-commit r267098)Gerolf Hoflehner2016-04-242-0/+264
| | | | | | | | | | | | | | | | | | | The original patch caused crashes because it could derefence a null pointer for SelectionDAGTargetInfo for targets that do not define it. Evaluates fmul+fadd -> fmadd combines and similar code sequences in the machine combiner. It adds support for float and double similar to the existing integer implementation. The key features are: - DAGCombiner checks whether it should combine greedily or let the machine combiner do the evaluation. This is only supported on ARM64. - It gives preference to throughput over latency: the heuristic used is to combine always in loops. The targets decides whether the machine combiner should optimize for throughput or latency. - Supports for fmadd, f(n)msub, fmla, fmls patterns - On by default at O3 ffast-math llvm-svn: 267328
* Revert "Verifier: Verify that each inlinable callsite of a ↵Adrian Prantl2016-04-243-66/+2
| | | | | | | | debug-info-bearing function" This reverts commit r267320 while investigating an OpenMP buildbot failure. llvm-svn: 267322
* Verifier: Verify that each inlinable callsite of a debug-info-bearing functionAdrian Prantl2016-04-243-2/+66
| | | | | | | | | | in a debug-info-bearing function has a debug location attached to it. Failure to do so causes an "!dbg attachment points at wrong subprogram for function" assertion failure when the inliner sets up inline scope info. rdar://problem/25878916 llvm-svn: 267320
* Reorganize GlobalValueSummary with a "Flags" bitfield.Mehdi Amini2016-04-243-19/+19
| | | | | | | | | | Right now it only contains the LinkageType, but will be extended with "hasSection", "isOptSize", "hasInlineAssembly", etc. Differential Revision: http://reviews.llvm.org/D19404 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267319
* Add a version field in the bitcode for the summaryMehdi Amini2016-04-247-0/+21
| | | | | | | Differential Revision: http://reviews.llvm.org/D19456 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267318
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