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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-25 19:27:18 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-25 19:27:18 +0000 |
| commit | 48ab526f12eca74e3dcf752c9f98dae3e92f173b (patch) | |
| tree | 03ec0a3311d51ad76a6ee47400fba1735e024eb5 /llvm/test | |
| parent | 621d3675cbb422283e6e858d778d3c2abfd5b929 (diff) | |
| download | bcm5719-llvm-48ab526f12eca74e3dcf752c9f98dae3e92f173b.tar.gz bcm5719-llvm-48ab526f12eca74e3dcf752c9f98dae3e92f173b.zip | |
AMDGPU: Add queue ptr intrinsic
llvm-svn: 267451
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll | 19 |
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll index ffba75d40ab..10dac31fec0 100644 --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll @@ -9,6 +9,7 @@ declare i32 @llvm.amdgcn.workitem.id.y() #0 declare i32 @llvm.amdgcn.workitem.id.z() #0 declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 +declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 ; HSA: define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { @@ -154,6 +155,15 @@ define void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 { ret void } +; HSA: define void @use_queue_ptr(i32 addrspace(1)* %ptr) #11 { +define void @use_queue_ptr(i32 addrspace(1)* %ptr) #1 { + %dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr() + %bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* + %val = load i32, i32 addrspace(2)* %bc + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + attributes #0 = { nounwind readnone } attributes #1 = { nounwind } @@ -168,3 +178,4 @@ attributes #1 = { nounwind } ; HSA: attributes #8 = { nounwind "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" } ; HSA: attributes #9 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" } ; HSA: attributes #10 = { nounwind "amdgpu-dispatch-ptr" } +; HSA: attributes #11 = { nounwind "amdgpu-queue-ptr" } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll new file mode 100644 index 00000000000..6bf871543ca --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s + +; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target + +; GCN-LABEL: {{^}}test: +; GCN: enable_sgpr_queue_ptr = 1 +; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 +define void @test(i32 addrspace(1)* %out) { + %queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 + %header_ptr = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* + %value = load i32, i32 addrspace(2)* %header_ptr + store i32 %value, i32 addrspace(1)* %out + ret void +} + +declare noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 + +attributes #0 = { nounwind readnone } |
