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* Refactor some more PDB reading code into DebugInfoPDB.Zachary Turner2016-04-261-17/+0
| | | | | | | Differential Revision: http://reviews.llvm.org/D19445 Reviewed By: David Majnemer llvm-svn: 267564
* [AMDGPU] Reserve VGPRs for trap handler usage if instructedKonstantin Zhuravlyov2016-04-261-0/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D19235 llvm-svn: 267563
* [AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton2016-04-261-0/+40
| | | | | | | | | | | | | | | Support for SDWA instructions for VOP1 and VOP2 encoding. Not done yet: - converters for support optional operands and modifiers - VOPC - sext() modifier - intrinsics - VOP2b (see vop_dpp.s) - V_MAC_F32 (see vop_dpp.s) Differential Revision: http://reviews.llvm.org/D19360 llvm-svn: 267553
* [X86] PR27502: Fix the LEA optimization pass.Andrey Turetskiy2016-04-262-1/+21
| | | | | | | | Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass. Differential Revision: http://reviews.llvm.org/D19409 llvm-svn: 267551
* [PowerPC] Add support for llvm.thread.pointerMarcin Koscielnicki2016-04-261-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D19304 llvm-svn: 267546
* [SPARC] [SSP] Add support for LOAD_STACK_GUARD.Marcin Koscielnicki2016-04-261-0/+33
| | | | | | | | This fixes PR22248 on sparc. Differential Revision: http://reviews.llvm.org/D19386 llvm-svn: 267545
* [SPARC] Add support for llvm.thread.pointer.Marcin Koscielnicki2016-04-261-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D19387 llvm-svn: 267544
* ThinLTOCodeGenerator: preserve linkonce when in "MustPreserved" setMehdi Amini2016-04-261-0/+8
| | | | | | | | | If the linker specifically requested for a linkonce to be preserved, we need to make sure we won't drop it even if all the uses in the current module disappear. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267543
* Revert "ARM: put correct symbol index on indirect pointers in __thread_ptr."Renato Golin2016-04-261-5/+1
| | | | | | This reverts commit r267488, as it broke some ARM buildbots. llvm-svn: 267541
* Symbolize operand bundle blocks for bcanalyzerSanjoy Das2016-04-261-0/+27
| | | | | | | | | | Reviewers: joker.eph Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19523 llvm-svn: 267524
* [AArch64] Expand v1i64 and v2i64 ctlz.Craig Topper2016-04-261-0/+28
| | | | | | The default is legal, which results in 'Cannot select' errors. llvm-svn: 267522
* [ARM] Expand vector ctlz_zero_undef so it becomes ctlz.Craig Topper2016-04-261-0/+62
| | | | | | The default is Legal, which results in 'Cannot select' errors. llvm-svn: 267521
* [ARM] Expand v1i64 and v2i64 ctlz.Craig Topper2016-04-261-0/+16
| | | | | | The default is legal, which results in 'Cannot select' errors. llvm-svn: 267520
* Tune basic block annotation algorithm.Dehao Chen2016-04-262-172/+251
| | | | | | | | | | | | | | | Summary: Instead of using maximum IR weight as the basic block weight, this patch uses the voting algorithm to find the most likely weight for the basic block. This can effectively avoid the cases when some IRs are annotated incorrectly due to code motion of the profiled binary. This patch also updates propagate.ll unittest to include discriminator in the input file so that it is testing something meaningful. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19301 llvm-svn: 267519
* [powerpc] mark JIT tests as UNSUPPORTED on powerpc64 big endianBill Seurer2016-04-2624-48/+72
| | | | | | | | | | | | | Some of the JIT tests began failing with "[llvm] r266663 - [Orc] Re-commit r266581 with fixes for MSVC, and format cleanups." on powerpc64 big endian. To get the buildbots running I am marking these as UNSUPPORTED for now. If this is fixed remove the UNSUPPORTED flag "powerpc64-unknown-linux-gnu". In r267516 I marked these as XFAIL but they succeed on some of the bots on stage1. llvm-svn: 267518
* Pass the test file in through stdin instead of by filename.Richard Trieu2016-04-261-1/+1
| | | | | | | | When passed in via filename, this test will fail if the path to the test has the strings "f1" and "f2" in somewhere. Pass the file through stdin to prevent test failures due to coincidences in path names. llvm-svn: 267517
* [powerpc] mark JIT tests as XFAIL on powerpc64 big endianBill Seurer2016-04-2624-24/+48
| | | | | | | | | | Some of the JIT tests began failing with "[llvm] r266663 - [Orc] Re-commit r266581 with fixes for MSVC, and format cleanups." on powerpc64 big endian. To get the buildbots running I am marking these as XFAIL for now. If this is fixed remove the XFAIL flag "powerpc64-unknown-linux-gnu". llvm-svn: 267516
* [SimplifyCFG] Preserve !llvm.mem.parallel_loop_access when mergingHal Finkel2016-04-261-0/+55
| | | | | | | | When SimplifyCFG merges identical instructions from both sides of a diamond, it can preserve !llvm.mem.parallel_loop_access (as it does with most of the other metadata). There's no real data or control dependency change in this case. llvm-svn: 267515
* [LoopVectorize] Don't consider conditional-load dereferenceability for ↵Hal Finkel2016-04-261-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | marked parallel loops I really thought we were doing this already, but we were not. Given this input: void Test(int *res, int *c, int *d, int *p) { for (int i = 0; i < 16; i++) res[i] = (p[i] == 0) ? res[i] : res[i] + d[i]; } we did not vectorize the loop. Even with "assume_safety" the check that we don't if-convert conditionally-executed loads (to protect against data-dependent deferenceability) was not elided. One subtlety: As implemented, it will still prefer to use a masked-load instrinsic (given target support) over the speculated load. The choice here seems architecture specific; the best option depends on how expensive the masked load is compared to a regular load. Ideally, using the masked load still reduces unnecessary memory traffic, and so should be preferred. If we'd rather do it the other way, flipping the order of the checks is easy. The LangRef is updated to make explicit that llvm.mem.parallel_loop_access also implies that if conversion is okay. Differential Revision: http://reviews.llvm.org/D19512 llvm-svn: 267514
* [WebAssembly] Account for implicit operands when computing operand indices.Dan Gohman2016-04-261-1/+7
| | | | llvm-svn: 267511
* [CodeGenPrepare] don't convert an unpredictable select into control flowSanjay Patel2016-04-261-5/+24
| | | | | | | Suggested in the review of D19488: http://reviews.llvm.org/D19488 llvm-svn: 267504
* PM: Port GlobalOpt to the new pass managerJustin Bogner2016-04-261-0/+1
| | | | llvm-svn: 267499
* [X86] Use LivePhysRegs in X86FixupBWInsts.Ahmed Bougacha2016-04-263-14/+19
| | | | | | | | | Kill-flags, which computeRegisterLiveness uses, are not reliable. LivePhysRegs is. Differential Revision: http://reviews.llvm.org/D19472 llvm-svn: 267495
* GlobalOpt: Convert a bunch of tests from grep to FileCheckJustin Bogner2016-04-2521-49/+66
| | | | llvm-svn: 267493
* Add check for "branch_weights" with prof metadataSanjay Patel2016-04-251-0/+24
| | | | | | | While we're here, fix the comment and variable names to make it clear that these are raw weights, not percentages. llvm-svn: 267491
* [Sparc] Fix double-float fabs and fneg on little endian CPUs.James Y Knight2016-04-252-77/+49
| | | | | | | | | | | | | | | | The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
* ARM: put correct symbol index on indirect pointers in __thread_ptr.Tim Northover2016-04-251-1/+5
| | | | | | Otherwise the linker has no idea what should be resolved. llvm-svn: 267488
* Optimize store of "bitcast" from vector to aggregate.Arch D. Robison2016-04-251-0/+74
| | | | | | | | | | | This patch is what was the "instcombine" portion of D14185, with an additional test added (see julia_pseudovec in test/Transforms/InstCombine/insert-val-extract-elem.ll). The patch causes instcombine to replace sequences of extractelement-insertvalue-store that act essentially like a bitcast followed by a store. Differential review: http://reviews.llvm.org/D14260 llvm-svn: 267482
* ARM: put extern __thread stubs in a special section.Tim Northover2016-04-252-0/+63
| | | | | | | The linker needs to know that the symbols are thread-local to do its job properly. llvm-svn: 267473
* Re-apply r267206 with a fix for the encoding problem: when the immediate ofQuentin Colombet2016-04-251-5/+52
| | | | | | | | | | | | | | | | | | log2(Mask) is smaller than 32, we must use the 32-bit variant because the 64-bit variant cannot encode it. Therefore, set the subreg part accordingly. [AArch64] Fix optimizeCondBranch logic. The opcode for the optimized branch does not depend on the size of the activate bits in the AND masks, but the AND opcode itself. Indeed, we need to use a X or W variant based on the AND variant not based on whether the mask fits into the related variant. Otherwise, we may end up using the W variant of the optimized branch for 64-bit register inputs! This fixes the last make check verifier issues for AArch64: PR27479. llvm-svn: 267465
* AMDGPU: Implement addrspacecastMatt Arsenault2016-04-253-22/+274
| | | | llvm-svn: 267452
* AMDGPU: Add queue ptr intrinsicMatt Arsenault2016-04-252-0/+30
| | | | llvm-svn: 267451
* [gold] Fix linkInModule and extend common.ll test.Evgeniy Stepanov2016-04-254-9/+29
| | | | | | | | | | Fix early exit from linkInModule. IRMover::move returns false on success and true on error. Add a few more cases of merged common linkage variables with different sizes and alignments. llvm-svn: 267437
* Fix typo from r267432.Chad Rosier2016-04-251-2/+2
| | | | llvm-svn: 267436
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-0/+9
| | | | | | Remember to svn add the new file. llvm-svn: 267435
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-9/+0
| | | | llvm-svn: 267434
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-251-0/+72
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
* [ValueTracking] Add an additional test case for r266767 where one operand is ↵Chad Rosier2016-04-251-0/+24
| | | | | | a const. llvm-svn: 267432
* Resubmit "Refactor raw pdb dumper into library"Zachary Turner2016-04-251-1/+1
| | | | | | | This fixes a number of endianness issues as well as an ODR violation that hopefully causes everything to be happy. llvm-svn: 267431
* [ValueTracking] Improve isImpliedCondition when the dominating cond is false.Chad Rosier2016-04-252-0/+389
| | | | llvm-svn: 267430
* dsymutil: Only warn about clang module DWO id mismatches in verbose mode.Adrian Prantl2016-04-251-1/+1
| | | | | | | | | | Until PR27449 (https://llvm.org/bugs/show_bug.cgi?id=27449) is fixed in clang this warning is pointless, since ASTFileSignatures will change randomly when a module is rebuilt. rdar://problem/25610919 llvm-svn: 267427
* add tests for potential CGP transform (PR27344)Sanjay Patel2016-04-251-0/+32
| | | | llvm-svn: 267426
* [PR27390] [CodeGen] Reject indexed loads in CombinerDAG.Marcin Koscielnicki2016-04-251-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | visitAND, when folding and (load) forgets to check which output of an indexed load is involved, happily folding the updated address output on the following testcase: target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" %typ = type { i32, i32 } define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) { %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1 %1 = load i32, i32* %b, align 4 %2 = ptrtoint i32* %b to i64 %3 = and i64 %2, -35184372088833 %4 = inttoptr i64 %3 to i32* %_msld = load i32, i32* %4, align 4 %zzz = add i32 %1, %_msld ret i32 %zzz } Fix this by checking ResNo. I've found a few more places that currently neglect to check for indexed load, and tightened them up as well, but I don't have test cases for them. In fact, they might not be triggerable at all, at least with current targets. Still, better safe than sorry. Differential Revision: http://reviews.llvm.org/D19202 llvm-svn: 267420
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-256-18/+2
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-2512-111/+0
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [x86] auto-generate checks for cmov testsSanjay Patel2016-04-251-14/+32
| | | | llvm-svn: 267417
* [WinEH] Update SplitAnalysis::computeLastSplitPoint to cope with multiple EH ↵David Majnemer2016-04-251-0/+67
| | | | | | | | | | | | | | | | | | | successors We didn't have logic to correctly handle CFGs where there was more than one EH-pad successor (these are novel with WinEH). There were situations where a register was live in one exceptional successor but not another but the code as written would only consider the first exceptional successor it found. This resulted in split points which were insufficiently early if an invoke was present. This fixes PR27501. N.B. This removes getLandingPadSuccessor. llvm-svn: 267412
* [ARM] Add support for the X asm constraintSilviu Baranga2016-04-252-0/+178
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for the X asm constraint. To do this, we lower the constraint to either a "w" or "r" constraint depending on the operand type (both constraints are supported on ARM). Fixes PR26493 Reviewers: t.p.northover, echristo, rengolin Subscribers: joker.eph, jgreenhalgh, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19061 llvm-svn: 267411
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-254-12/+56
| | | | | | | | | | | | | Added hwreg(reg[,offset,width]) syntax. Default offset = 0, default width = 32. Possibility to specify 16-bit immediate kept. Added out-of-range checks. Disassembling is always to hwreg(...) format. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19329 llvm-svn: 267410
* [Hexagon] Correctly set "Flags" in ELF headerKrzysztof Parzyszek2016-04-251-0/+9
| | | | llvm-svn: 267397
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