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* [CGP] Fix crash on i96 bit multiplyPhilip Reames2017-10-301-0/+10
| | | | | | | | Issue found by llvm-isel-fuzzer on OSS fuzz, https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3725 If anyone actually cares about > 64 bit arithmetic, there's a lot more to do in this area. There's a bunch of obviously wrong code in the same function. I don't have the time to fix all of them and am just using this to understand what the workflow for fixing fuzzer cases might look like. llvm-svn: 316967
* InferAddressSpaces: Fix bug about replacing addrspacecastYaxun Liu2017-10-301-0/+13
| | | | | | | | | | | | | | InferAddressSpaces assumes the pointee type of addrspacecast is the same as the operand, which is not always true and causes invalid IR. This bug cause build failure in HCC. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39432 llvm-svn: 316957
* [X86] Add AVX512 support to fast isel's X86ChooseCmpOpcode.Craig Topper2017-10-302-0/+2
| | | | llvm-svn: 316955
* [NewGVN] Stop assuming PHI args ordering when looking at phi-of-ops.Davide Italiano2017-10-301-0/+70
| | | | | | | | It's not guaranteed. There's a bug open to sort them in predecessor order, but it won't happen anytime soon. In the meanwhile, passes will have to do an O(#preds) scan. Such is life. llvm-svn: 316953
* Revert "[PowerPC] Try to simplify a Swap if it feeds a Splat"Stefan Pintilie2017-10-302-136/+2
| | | | | | | | | | Revert r316478. A test case has failed. Will recommit this change once we find and fix the failure. This reverts commit 7c330fabaedaba3d02c58bc3cc1198896c895f34. llvm-svn: 316952
* [SelectionDAG] Add VSELECT demanded elts support to computeKnownBits Simon Pilgrim2017-10-301-20/+4
| | | | llvm-svn: 316947
* X86 Tests: Update the variable-index permute tests with FP types. NFC.Zvi Rackover2017-10-303-0/+456
| | | | | | These cases will be addressed in a future update to D39126. llvm-svn: 316946
* [X86][SSE] Add another computeKnownBits test showing missing VSELECT ↵Simon Pilgrim2017-10-301-0/+44
| | | | | | demandedelts support llvm-svn: 316945
* [SelectionDAG] Add VSELECT support to computeKnownBits Simon Pilgrim2017-10-302-29/+29
| | | | llvm-svn: 316944
* [X86][SSE] computeKnownBits tests showing missing VSELECT demandedelts support Simon Pilgrim2017-10-301-0/+48
| | | | llvm-svn: 316940
* [X86][AVX512] Cleanup scheduler tests - split GENERIC and SKX targetsSimon Pilgrim2017-10-302-8923/+16710
| | | | llvm-svn: 316938
* [SelectionDAG] Add SELECT demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-301-36/+7
| | | | llvm-svn: 316933
* [X86][SSE] ComputeNumSignBits tests showing missing VSELECT demandedelts ↵Simon Pilgrim2017-10-301-0/+107
| | | | | | support llvm-svn: 316932
* [X86][AVX] Add missing vcvtpd2dq/vcvtps2dq scheduling testsSimon Pilgrim2017-10-301-14/+142
| | | | llvm-svn: 316926
* [X86][SSE] Add clflush scheduling testSimon Pilgrim2017-10-301-0/+61
| | | | llvm-svn: 316925
* [X86][AVX512] Adding a pattern for broadcastm intrinsic.Jina Nahias2017-10-301-57/+9
| | | | | | | Differential Revision: https://reviews.llvm.org/D38312 Change-Id: I71c8605a8e4c98013ef25289694afc5cfd46bb0b llvm-svn: 316921
* [PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song2017-10-302-32/+32
| | | | | | | | | | | | Summary: The two 32-bit words were swapped. Update a test omitted in reverted r316270. Reviewers: jtony, aaron.ballman Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D39163 llvm-svn: 316916
* [X86] Make sure we don't create locked inc/dec instructions when the carry ↵Craig Topper2017-10-301-28/+42
| | | | | | | | | | | | | | | | | | | | | | | flag is being used. Summary: INC/DEC don't update the carry flag so we need to make sure we don't try to use it. This patch introduces new X86ISD opcodes for locked INC/DEC. Teaches lowerAtomicArithWithLOCK to emit these nodes if INC/DEC is not slow or the function is being optimized for size. An additional flag is added that allows the INC/DEC to be disabled if the caller determines that the carry flag is being requested. The test_sub_1_cmp_1_setcc_ugt test is currently showing this bug. The other test case changes are recovering cases that were regressed in r316860. This should fully fix PR35068 finishing the fix started in r316860. Reviewers: RKSimon, zvi, spatel Reviewed By: zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39411 llvm-svn: 316913
* [X86] Remove AVX512 early out from X86FastISel::X86SelectCmp.Craig Topper2017-10-304-127/+152
| | | | | | This shouldn't be needed anymore since i1 isn't a legal type. llvm-svn: 316912
* [X86] Regenerate test using update_llc_test_checks.pyCraig Topper2017-10-301-32/+439
| | | | llvm-svn: 316911
* [PassManager, SimplifyCFG] add test for PR34603 / D38566; NFCSanjay Patel2017-10-301-1/+41
| | | | | | Sinking common insts and converting to select early can inhibit better folds in other passes. llvm-svn: 316908
* [AMDGPU] Emit metadata for hidden arguments for kernel enqueueYaxun Liu2017-10-303-1/+159
| | | | | | | | | | | | | Identifies kernels which performs device side kernel enqueues and emit metadata for the associated hidden kernel arguments. Such kernels are marked with calls-enqueue-kernel function attribute by AMDGPUOpenCLEnqueueKernelLowering pass and later on hidden kernel arguments metadata HiddenDefaultQueue and HiddenCompletionAction are emitted for them. Differential Revision: https://reviews.llvm.org/D39255 llvm-svn: 316907
* [CodeGen][ExpandMemcmp] Allow memcmp to expand to vector loads (2).Clement Courbet2017-10-303-251/+640
| | | | | | | | | | | | - Targets that want to support memcmp expansions now return the list of supported load sizes. - Expansion codegen does not assume that all power-of-two load sizes smaller than the max load size are valid. For examples, this is not the case for x86(32bit)+sse2. Fixes PR34887. llvm-svn: 316905
* [GlobalISel|ARM] : Allow legalizing G_FSUBJaved Absar2017-10-304-0/+225
| | | | | | | | Adding support for VSUB. Reviewed by: @rovka Differential Revision: https://reviews.llvm.org/D39261 llvm-svn: 316902
* Invalid used of 'w' suffix on push and pop using 64-bit register.Andrew V. Tischenko2017-10-301-4/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D38626 llvm-svn: 316898
* [ARM GlobalISel] Fixup r316572. NFCDiana Picus2017-10-301-9/+0
| | | | | | Just missed a few spots... llvm-svn: 316897
* Revert "[X86][AVX512] Adding a pattern for broadcastm intrinsic."Jina Nahias2017-10-301-9/+57
| | | | | | | This reverts commit r316890. Change-Id: I683cceee9848ef309b452293086b1f26a941950d llvm-svn: 316894
* Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.Florian Hahn2017-10-301-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version of the patch includes a fix addressing a stage2 LTO buildbot failure and addressed some additional nits. Original commit message: This updates the SCCP solver to use of the ValueElement lattice for parameters, which provides integer range information. The range information is used to remove unneeded icmp instructions. For the following function, f() can be optimized to ret i32 2 with this change source_filename = "sccp.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind readnone uwtable define i32 @main() local_unnamed_addr #0 { entry: %call = tail call fastcc i32 @f(i32 1) %call1 = tail call fastcc i32 @f(i32 47) %add3 = add nsw i32 %call, %call1 ret i32 %add3 } ; Function Attrs: noinline norecurse nounwind readnone uwtable define internal fastcc i32 @f(i32 %x) unnamed_addr #1 { entry: %c1 = icmp sle i32 %x, 100 %cmp = icmp sgt i32 %x, 300 %. = select i1 %cmp, i32 1, i32 2 ret i32 %. } attributes #1 = { noinline } Reviewers: davide, sanjoy, efriedma, dberlin Reviewed By: davide, dberlin Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D36656 llvm-svn: 316891
* [X86][AVX512] Adding a pattern for broadcastm intrinsic.Jina Nahias2017-10-301-57/+9
| | | | | | | Differential Revision: https://reviews.llvm.org/D38312 Change-Id: I6551fb13879e098aed74de410e29815cf37d9ab5 llvm-svn: 316890
* [IRCE][NFC] Store Length as SCEV in RangeCheck instead of ValueMax Kazantsev2017-10-301-1/+1
| | | | llvm-svn: 316889
* Revert r316887 to fix buildbot failures.Florian Hahn2017-10-301-135/+0
| | | | llvm-svn: 316888
* Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.Florian Hahn2017-10-301-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version of the patch includes a fix addressing a stage2 LTO buildbot failure and addressed some additional nits. Original commit message: This updates the SCCP solver to use of the ValueElement lattice for parameters, which provides integer range information. The range information is used to remove unneeded icmp instructions. For the following function, f() can be optimized to ret i32 2 with this change source_filename = "sccp.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind readnone uwtable define i32 @main() local_unnamed_addr #0 { entry: %call = tail call fastcc i32 @f(i32 1) %call1 = tail call fastcc i32 @f(i32 47) %add3 = add nsw i32 %call, %call1 ret i32 %add3 } ; Function Attrs: noinline norecurse nounwind readnone uwtable define internal fastcc i32 @f(i32 %x) unnamed_addr #1 { entry: %c1 = icmp sle i32 %x, 100 %cmp = icmp sgt i32 %x, 300 %. = select i1 %cmp, i32 1, i32 2 ret i32 %. } attributes #1 = { noinline } Reviewers: davide, sanjoy, efriedma, dberlin Reviewed By: davide, dberlin Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D36656 llvm-svn: 316887
* [SelectionDAG] Add SEXT/AND/XOR/Or demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-23/+15
| | | | llvm-svn: 316875
* [X86][SSE] Split ComputeNumSignBits SEXT/AND/XOR/OR demandedelts testSimon Pilgrim2017-10-291-17/+65
| | | | | | Max depth was being exceeded which could prevent some combines working llvm-svn: 316871
* [(new) Pass Manager] instantiate SimplifyCFG with the same options as the old PMSanjay Patel2017-10-291-54/+25
| | | | | | | | | | | | The old PM sets the options of what used to be known as "latesimplifycfg" on the instantiation after the vectorizers have run, so that's what we'redoing here. FWIW, there's a later SimplifyCFGPass instantiation in both PMs where we do not set the "late" options. I'm not sure if that's intentional or not. Differential Revision: https://reviews.llvm.org/D39407 llvm-svn: 316869
* [X86][SSE] ComputeNumSignBits tests showing missing SEXT/AND/XOR/OR ↵Simon Pilgrim2017-10-291-0/+68
| | | | | | demandedelts support llvm-svn: 316868
* [SelectionDAG] Add SRA/SHL demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-291-24/+14
| | | | | | Introduce a isConstOrDemandedConstSplat helper function that can recognise a constant splat build vector for at least the demanded elts we care about. llvm-svn: 316866
* [X86][SSE] ComputeNumSignBits tests showing missing SHL/SRA demandedelts ↵Simon Pilgrim2017-10-291-3/+90
| | | | | | support llvm-svn: 316865
* [X86] Add a slow-incdec command line to atomic-eflags-reuse.llCraig Topper2017-10-291-38/+82
| | | | | | I believe the test_sub_1_cmp_1_setcc_ugt test case is being miscompiled in the fast inc/dec case. llvm-svn: 316864
* [X86] Remove combine that turns X86ISD::LSUB into X86ISD::LADD. Update ↵Craig Topper2017-10-291-3/+3
| | | | | | | | | | | | patterns that depended on this. If the carry flag is being used, this transformation isn't safe. This does prevent some test cases from using DEC now, but I'll try to look into that separately. Fixes PR35068. llvm-svn: 316860
* [X86] Add AVX512 support to X86FastISel::X86SelectFPExt and ↵Craig Topper2017-10-291-0/+1
| | | | | | X86FastISel::X86SelectFPTrunc. llvm-svn: 316856
* [X86] Use update_llc_test_checks.py to regenerate ↵Craig Topper2017-10-291-16/+37
| | | | | | fast-isel-int-float-conversion.ll llvm-svn: 316855
* [X86] Use update_llc_test_checks.py to regenerate fast-isel-fptrunc-fpext.llCraig Topper2017-10-291-18/+39
| | | | llvm-svn: 316854
* [X86] Add AVX512 support to X86FastISel::X86MaterializeFPCraig Topper2017-10-291-0/+2
| | | | llvm-svn: 316853
* [SelectionDAG] Add support for INSERT_SUBVECTOR to computeKnownBitsSimon Pilgrim2017-10-281-12/+8
| | | | llvm-svn: 316847
* [X86][SSE] Combine 128-bit target shuffles to PACKSS/PACKUS.Simon Pilgrim2017-10-283-45/+29
| | | | llvm-svn: 316845
* [SimplifyCFG] use pass options and remove the latesimplifycfg passSanjay Patel2017-10-2813-36/+75
| | | | | | | | | | | | | | | | | This is no-functional-change-intended. This is repackaging the functionality of D30333 (defer switch-to-lookup-tables) and D35411 (defer folding unconditional branches) with pass parameters rather than a named "latesimplifycfg" pass. Now that we have individual options to control the functionality, we could decouple when these fire (but that's an independent patch if desired). The next planned step would be to add another option bit to disable the sinking transform mentioned in D38566. This should also make it clear that the new pass manager needs to be updated to limit simplifycfg in the same way as the old pass manager. Differential Revision: https://reviews.llvm.org/D38631 llvm-svn: 316835
* [X86] Correct the alignments on the aligned test cases in ↵Craig Topper2017-10-281-24/+24
| | | | | | fast-isel-vecload.ll to make sure they test selection of aligned loads. llvm-svn: 316833
* [SelectionDAG] Support 'bit preserving' floating points bitcasts on ↵Simon Pilgrim2017-10-287-452/+340
| | | | | | | | | | | | computeKnownBits/ComputeNumSignBits For cases where we know the floating point representations match the bitcasted integer equivalent, allow bitcasting to these types. This is especially useful for the X86 floating point compare results which return all/zero bits but as a floating point type. Differential Revision: https://reviews.llvm.org/D39289 llvm-svn: 316831
* [X86] Add avx command lines to fast-isel-constpool.ll to improve coverage.Craig Topper2017-10-281-0/+26
| | | | llvm-svn: 316829
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